[PATCH] drm/amdgpu/sriov: Use kiq to copy the gpu clock

[Deng, Emily]

[AMD Official Use Only - Internal Distribution Only]

Thanks Alex and Christian. Already  renamed it according your request. Please help review.

Best wishes
Emily Deng



>-----Original Message-----
>From: Alex Deucher <alexdeucher at gmail.com>
>Sent: Wednesday, February 26, 2020 10:30 PM
>To: Deng, Emily <Emily.Deng at amd.com>
>Cc: amd-gfx list <amd-gfx at lists.freedesktop.org>
>Subject: Re: [PATCH] drm/amdgpu/sriov: Use kiq to copy the gpu clock
>
>On Tue, Feb 25, 2020 at 11:34 PM Emily Deng <Emily.Deng at amd.com> wrote:
>>
>> For vega10 sriov, the register is blocked, use copy data command to
>> fix the issue.
>>
>> Signed-off-by: Emily Deng <Emily.Deng at amd.com>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 68
>> +++++++++++++++++++++++++++++------
>>  1 file changed, 58 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 1c7a16b..71df0d9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -3963,6 +3963,63 @@ static int gfx_v9_0_soft_reset(void *handle)
>>         return 0;
>>  }
>>
>> +static uint64_t amdgpu_kiq_read_clock(struct amdgpu_device *adev)
>
>Please name this function gfx_v9_0_kiq_read_clock for consistency.
>
>
>> +{
>> +       signed long r, cnt = 0;
>> +       unsigned long flags;
>> +       uint32_t seq;
>> +       struct amdgpu_kiq *kiq = &adev->gfx.kiq;
>> +       struct amdgpu_ring *ring = &kiq->ring;
>> +
>> +       BUG_ON(!ring->funcs->emit_rreg);
>> +
>> +       spin_lock_irqsave(&kiq->ring_lock, flags);
>> +       amdgpu_ring_alloc(ring, 32);
>> +       amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
>> +       amdgpu_ring_write(ring, 9 |     /* src: register*/
>
>Is src 9 the counter?
Yes, it is gpu counter.
>
>Assuming that is correct, with the naming fixed:
>Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
>
>> +                               (5 << 8) |      /* dst: memory */
>> +                               (1 << 16) |     /* count sel */
>> +                               (1 << 20));     /* write confirm */
>> +       amdgpu_ring_write(ring, 0);
>> +       amdgpu_ring_write(ring, 0);
>> +       amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
>> +                               kiq->reg_val_offs * 4));
>> +       amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
>> +                               kiq->reg_val_offs * 4));
>> +       amdgpu_fence_emit_polling(ring, &seq);
>> +       amdgpu_ring_commit(ring);
>> +       spin_unlock_irqrestore(&kiq->ring_lock, flags);
>> +
>> +       r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
>> +
>> +       /* don't wait anymore for gpu reset case because this way may
>> +        * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
>> +        * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
>> +        * never return if we keep waiting in virt_kiq_rreg, which cause
>> +        * gpu_recover() hang there.
>> +        *
>> +        * also don't wait anymore for IRQ context
>> +        * */
>> +       if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
>> +               goto failed_kiq_read;
>> +
>> +       might_sleep();
>> +       while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
>> +               msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
>> +               r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
>> +       }
>> +
>> +       if (cnt > MAX_KIQ_REG_TRY)
>> +               goto failed_kiq_read;
>> +
>> +       return (uint64_t)adev->wb.wb[kiq->reg_val_offs] |
>> +               (uint64_t)adev->wb.wb[kiq->reg_val_offs + 1 ] <<
>> + 32ULL;
>> +
>> +failed_kiq_read:
>> +       pr_err("failed to read gpu clock\n");
>> +       return ~0;
>> +}
>> +
>>  static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device
>> *adev)  {
>>         uint64_t clock;
>> @@ -3970,16 +4027,7 @@ static uint64_t
>gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>>         amdgpu_gfx_off_ctrl(adev, false);
>>         mutex_lock(&adev->gfx.gpu_clock_mutex);
>>         if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
>> -               uint32_t tmp, lsb, msb, i = 0;
>> -               do {
>> -                       if (i != 0)
>> -                               udelay(1);
>> -                       tmp = RREG32_SOC15(GC, 0,
>mmRLC_REFCLOCK_TIMESTAMP_MSB);
>> -                       lsb = RREG32_SOC15(GC, 0,
>mmRLC_REFCLOCK_TIMESTAMP_LSB);
>> -                       msb = RREG32_SOC15(GC, 0,
>mmRLC_REFCLOCK_TIMESTAMP_MSB);
>> -                       i++;
>> -               } while (unlikely(tmp != msb) && (i < adev->usec_timeout));
>> -               clock = (uint64_t)lsb | ((uint64_t)msb << 32ULL);
>> +               clock = amdgpu_kiq_read_clock(adev);
>>         } else {
>>                 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
>>                 clock = (uint64_t)RREG32_SOC15(GC, 0,
>> mmRLC_GPU_CLOCK_COUNT_LSB) |
>> --
>> 2.7.4
>>
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>gfx&data=02%7C01%7CEm
>>
>ily.Deng%40amd.com%7C9ebe490f88644de35b9a08d7bac85d1c%7C3dd8961fe4
>884e
>>
>608e11a82d994e183d%7C0%7C0%7C637183242027868417&sdata=6mdbo
>Q%2BeeH
>> KeQXnEm%2B6lFfMuBnMSfGhxpWXHjfg6Vso%3D&reserved=0
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From: "Deng, Emily" <Emily.Deng at amd.com>
Subject: [PATCH v2] drm/amdgpu/sriov: Use kiq to copy the gpu clock
Date: Thu, 27 Feb 2020 01:48:15 +0000
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URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20200227/0068ffe0/attachment-0001.eml>