[PATCH 1/2] amd/amdgpu/sriov enable onevf mode for ARCTURUS VF
Quan, Evan
Evan.Quan at amd.com
Thu Jan 2 08:03:57 UTC 2020
Acked-by: Evan Quan <evan.quan at amd.com>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Jack
> Zhang
> Sent: Thursday, January 2, 2020 3:44 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Zhang, Jack (Jian) <Jack.Zhang1 at amd.com>
> Subject: [PATCH 1/2] amd/amdgpu/sriov enable onevf mode for ARCTURUS VF
>
> Before, initialization of smu ip block would be skipped for sriov ASICs. But if
> there's only one VF being used, guest driver should be able to dump some HW
> info such as clks, temperature,etc.
>
> To solve this, now after onevf mode is enabled, host driver will notify guest. If
> it's onevf mode, guest will do smu hw_init and skip some steps in normal smu
> hw_init flow because host driver has already done it for smu.
>
> With this fix, guest app can talk with smu and dump hw information from smu.
>
> v2: refine the logic for pm_enabled.Skip hw_init by not changing pm_enabled.
> v3: refine is_support_sw_smu and fix some indentation issue.
>
> Signed-off-by: Jack Zhang <Jack.Zhang1 at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +-
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 98 ++++++++++++++++------
> --------
> 3 files changed, 56 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 0d842a1..5341905 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -1454,7 +1454,8 @@ static int psp_np_fw_load(struct psp_context *psp)
> || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
> || ucode->ucode_id ==
> AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
> || ucode->ucode_id ==
> AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
> - || ucode->ucode_id ==
> AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM))
> + || ucode->ucode_id ==
> AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
> + || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
> /*skip ucode loading in SRIOV VF */
> continue;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 6129fab..26e1c8c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -826,8 +826,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev,
> &dce_virtual_ip_block);
> amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
> amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
> - if (!amdgpu_sriov_vf(adev))
> - amdgpu_device_ip_block_add(adev,
> &smu_v11_0_ip_block);
> + amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
>
> if (unlikely(adev->firmware.load_type ==
> AMDGPU_FW_LOAD_DIRECT))
> amdgpu_device_ip_block_add(adev,
> &vcn_v2_5_ip_block); diff --git
> a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 4ed8bdc..4b96937 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -531,7 +531,7 @@ bool is_support_sw_smu(struct amdgpu_device *adev)
> if (adev->asic_type == CHIP_VEGA20)
> return (amdgpu_dpm == 2) ? true : false;
> else if (adev->asic_type >= CHIP_ARCTURUS) {
> - if (amdgpu_sriov_vf(adev))
> + if
> (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
> return false;
> else
> return true;
> @@ -1061,28 +1061,27 @@ static int smu_smc_table_hw_init(struct
> smu_context *smu,
> }
>
> /* smu_dump_pptable(smu); */
> + if (!amdgpu_sriov_vf(adev)) {
> + /*
> + * Copy pptable bo in the vram to smc with SMU MSGs such as
> + * SetDriverDramAddr and TransferTableDram2Smu.
> + */
> + ret = smu_write_pptable(smu);
> + if (ret)
> + return ret;
>
> - /*
> - * Copy pptable bo in the vram to smc with SMU MSGs such as
> - * SetDriverDramAddr and TransferTableDram2Smu.
> - */
> - ret = smu_write_pptable(smu);
> - if (ret)
> - return ret;
> -
> - /* issue Run*Btc msg */
> - ret = smu_run_btc(smu);
> - if (ret)
> - return ret;
> -
> - ret = smu_feature_set_allowed_mask(smu);
> - if (ret)
> - return ret;
> -
> - ret = smu_system_features_control(smu, true);
> - if (ret)
> - return ret;
> + /* issue Run*Btc msg */
> + ret = smu_run_btc(smu);
> + if (ret)
> + return ret;
> + ret = smu_feature_set_allowed_mask(smu);
> + if (ret)
> + return ret;
>
> + ret = smu_system_features_control(smu, true);
> + if (ret)
> + return ret;
> + }
> if (adev->asic_type != CHIP_ARCTURUS) {
> ret = smu_notify_display_change(smu);
> if (ret)
> @@ -1135,8 +1134,9 @@ static int smu_smc_table_hw_init(struct
> smu_context *smu,
> /*
> * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for
> tools.
> */
> - ret = smu_set_tool_table_location(smu);
> -
> + if (!amdgpu_sriov_vf(adev)) {
> + ret = smu_set_tool_table_location(smu);
> + }
> if (!smu_is_dpm_running(smu))
> pr_info("dpm has been disabled\n");
>
> @@ -1248,6 +1248,9 @@ static int smu_hw_init(void *handle)
> smu_set_gfx_cgpg(&adev->smu, true);
> }
>
> + if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
> + return 0;
> +
> if (!smu->pm_enabled)
> return 0;
>
> @@ -1300,37 +1303,42 @@ static int smu_hw_fini(void *handle)
> struct smu_table_context *table_context = &smu->smu_table;
> int ret = 0;
>
> + if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
> + return 0;
> +
> if (adev->flags & AMD_IS_APU) {
> smu_powergate_sdma(&adev->smu, true);
> smu_powergate_vcn(&adev->smu, true);
> smu_powergate_jpeg(&adev->smu, true);
> }
>
> - ret = smu_stop_thermal_control(smu);
> - if (ret) {
> - pr_warn("Fail to stop thermal control!\n");
> - return ret;
> - }
> -
> - /*
> - * For custom pptable uploading, skip the DPM features
> - * disable process on Navi1x ASICs.
> - * - As the gfx related features are under control of
> - * RLC on those ASICs. RLC reinitialization will be
> - * needed to reenable them. That will cost much more
> - * efforts.
> - *
> - * - SMU firmware can handle the DPM reenablement
> - * properly.
> - */
> - if (!smu->uploading_custom_pp_table ||
> - !((adev->asic_type >= CHIP_NAVI10) &&
> - (adev->asic_type <= CHIP_NAVI12))) {
> - ret = smu_stop_dpms(smu);
> + if (!amdgpu_sriov_vf(adev)){
> + ret = smu_stop_thermal_control(smu);
> if (ret) {
> - pr_warn("Fail to stop Dpms!\n");
> + pr_warn("Fail to stop thermal control!\n");
> return ret;
> }
> +
> + /*
> + * For custom pptable uploading, skip the DPM features
> + * disable process on Navi1x ASICs.
> + * - As the gfx related features are under control of
> + * RLC on those ASICs. RLC reinitialization will be
> + * needed to reenable them. That will cost much more
> + * efforts.
> + *
> + * - SMU firmware can handle the DPM reenablement
> + * properly.
> + */
> + if (!smu->uploading_custom_pp_table ||
> + !((adev->asic_type >= CHIP_NAVI10) &&
> + (adev->asic_type <= CHIP_NAVI12))) {
> + ret = smu_stop_dpms(smu);
> + if (ret) {
> + pr_warn("Fail to stop Dpms!\n");
> + return ret;
> + }
> + }
> }
>
> kfree(table_context->driver_pptable);
> --
> 2.7.4
>
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