[PATCH 5/5] drm/amd/amdgpu: L1 Policy(5/5) - removed IH_CHICKEN from VF

[Deng, Emily]

[AMD Official Use Only - Internal Distribution Only]

Series are Reviewed-by: Emily Deng <Emily.Deng at amd.com>

>-----Original Message-----
>From: Jane Jian <Jane.Jian at amd.com>
>Sent: Friday, January 3, 2020 5:57 PM
>To: amd-gfx at lists.freedesktop.org; Deng, Emily <Emily.Deng at amd.com>; Liu, Leo
><Leo.Liu at amd.com>
>Cc: Jian,JaneQiang) <Jane.Jian at amd.com>; Luo, Zhigang
><Zhigang.Luo at amd.com>; Jian,JaneQiang) <Jane.Jian at amd.com>
>Subject: [PATCH 5/5] drm/amd/amdgpu: L1 Policy(5/5) - removed IH_CHICKEN
>from VF
>
>From: Zhigang Luo <zhigang.luo at amd.com>
>
>Signed-off-by: Zhigang Luo <zhigang.luo at amd.com>
>Signed-off-by: Jane Jian <jane.jian at amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 22 ++++++++++++----------
> 1 file changed, 12 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>index 5cb7e231de5f..d9e331084ea0 100644
>--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>@@ -234,16 +234,9 @@ static int vega10_ih_irq_init(struct amdgpu_device
>*adev)
> 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) &
>0xff);
>
> 	ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
>-	ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
> 	ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
>-	if (adev->irq.ih.use_bus_addr) {
>-		ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
>MC_SPACE_GPA_ENABLE, 1);
>-	} else {
>-		ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
>MC_SPACE_FBPA_ENABLE, 1);
>-	}
> 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
> 				   !!adev->irq.msi_enabled);
>-
> 	if (amdgpu_sriov_vf(adev)) {
> 		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL,
>ih_rb_cntl)) {
> 			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
>@@ -253,10 +246,19 @@ static int vega10_ih_irq_init(struct amdgpu_device
>*adev)
> 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> 	}
>
>-	if ((adev->asic_type == CHIP_ARCTURUS
>-		&& adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)
>-		|| adev->asic_type == CHIP_RENOIR)
>+	if ((adev->asic_type == CHIP_ARCTURUS &&
>+	     adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
>+	    adev->asic_type == CHIP_RENOIR) {
>+		ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
>+		if (adev->irq.ih.use_bus_addr) {
>+			ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
>+						   MC_SPACE_GPA_ENABLE, 1);
>+		} else {
>+			ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
>+						   MC_SPACE_FBPA_ENABLE, 1);
>+		}
> 		WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
>+	}
>
> 	/* set the writeback address whether it's enabled or not */
> 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
>--
>2.17.1