No idea either why that was done.
Anyway patch is Acked-by: Christian König <christian.koenig at amd.com>.
Regards,
Christian.
Am 06.01.20 um 20:16 schrieb Felix Kuehling:
> This patch is
>
> Acked-by: Felix Kuehling <Felix.Kuehling at amd.com>
>
> I don't really know why the mask was different on GFXv10. I suspect it
> was laziness/simplicity of not having the gap at engines 2,3. If we
> don't have as many rings on GFXv10 ASICs we probably don't need
> engines 0,1.
>
> Regards,
> Felix
>
> On 2020-01-06 1:35 p.m., Alex Deucher wrote:
>> Rather than open coding it. This also changes the free masks
>> to better reflect the usage by other components.
>>
>> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
>> ---
>>
>> We always started at invalidation engine 4 on gmc10. Was there a
>> reason for that? I would have figured it would follow the same
>> model as older asics. I can make this more flexiable if so.
>>
>>
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 19 ++++---------------
>> 2 files changed, 5 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>> index d6901b274790..5884ab590486 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>> @@ -335,7 +335,7 @@ void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
>> }
>> /*
>> - * The latest engine allocation on gfx9 is:
>> + * The latest engine allocation on gfx9/10 is:
>> * Engine 2, 3: firmware
>> * Engine 0, 1, 4~16: amdgpu ring,
>> * subject to change when ring number changes
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> index f5725336a5f2..da9765ff45d6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> @@ -564,22 +564,11 @@ static int gmc_v10_0_early_init(void *handle)
>> static int gmc_v10_0_late_init(void *handle)
>> {
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> - unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
>> - unsigned i;
>> -
>> - for(i = 0; i < adev->num_rings; ++i) {
>> - struct amdgpu_ring *ring = adev->rings[i];
>> - unsigned vmhub = ring->funcs->vmhub;
>> -
>> - ring->vm_inv_eng = vm_inv_eng[vmhub]++;
>> - dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub
>> %u\n",
>> - ring->idx, ring->name, ring->vm_inv_eng,
>> - ring->funcs->vmhub);
>> - }
>> + int r;
>> - /* Engine 17 is used for GART flushes */
>> - for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
>> - BUG_ON(vm_inv_eng[i] > 17);
>> + r = amdgpu_gmc_allocate_vm_inv_eng(adev);
>> + if (r)
>> + return r;
>> return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
>> }
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