[PATCH 1/2] drm/amdgpu/vcn2.5: fix PSP FW loading for the second instance

James Zhu jamesz at amd.com
Tue Jan 7 21:17:59 UTC 2020


Reviewed-by: James Zhu <James.Zhu at amd.com> for the series

On 2020-01-07 3:55 p.m., Leo Liu wrote:
> ucodes for instances are from different location
>
> Signed-off-by: Leo Liu <leo.liu at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 4ea8e20ed15d..fa9024988918 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -384,9 +384,9 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
>   		/* cache window 0: fw */
>   		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>   			WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> -				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
> +				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo));
>   			WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> -				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
> +				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi));
>   			WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
>   			offset = 0;
>   		} else {


More information about the amd-gfx mailing list