[PATCH 2/2] drm/amdgpu: reading CP_MEM_SLP_CNTL register using RREG32_KIQ macro

[Huang Rui]

On Mon, Jan 13, 2020 at 06:16:22PM +0800, chen gong wrote:
> Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to
> hang when GPU is in "gfxoff" state.
> 
> Signed-off-by: chen gong <curry.gong at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index e3d466b..a666086 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4702,7 +4702,7 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
>  		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
>  
>  	/* AMD_CG_SUPPORT_GFX_CP_LS */
> -	data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
> +	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));

We should use kiq instead of mmio access for the whole
gfx_v9_0_get_clockgating_state().

Thanks,
Ray

>  	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
>  		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
>  
> -- 
> 2.7.4
> 
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