[PATCH 4/7] drm/amdgpu: replace kcq enable function on gfx_v9

[Felix Kuehling]

Can you include kcq_disable in the patch as well?

Thanks,
   Felix

On 2020-01-11 1:39 p.m., Alex Sierra wrote:
> [Why]
> There's a HW-indpendent function that enables kcq. This function uses
> the kiq_pm4_funcs implementation.
>
> [How]
> Local kcq enable function removed and replace it by the generic kcq
> enable under amdgpu_gfx
>
> Change-Id: I7709bdba93742c234941a5936c82eb67e346077c
> Signed-off-by: Alex Sierra <alex.sierra at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 70 +--------------------------
>   1 file changed, 1 insertion(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 5be6fab55b73..7219eacad9ce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3252,74 +3252,6 @@ static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
>   	WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
>   }
>   
> -static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
> -{
> -	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
> -	uint64_t queue_mask = 0;
> -	int r, i;
> -
> -	for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
> -		if (!test_bit(i, adev->gfx.mec.queue_bitmap))
> -			continue;
> -
> -		/* This situation may be hit in the future if a new HW
> -		 * generation exposes more than 64 queues. If so, the
> -		 * definition of queue_mask needs updating */
> -		if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
> -			DRM_ERROR("Invalid KCQ enabled: %d\n", i);
> -			break;
> -		}
> -
> -		queue_mask |= (1ull << i);
> -	}
> -
> -	r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 8);
> -	if (r) {
> -		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
> -		return r;
> -	}
> -
> -	/* set resources */
> -	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
> -	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
> -			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
> -	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */
> -	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */
> -	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */
> -	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */
> -	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
> -	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
> -	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> -		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
> -		uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
> -		uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
> -
> -		amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
> -		/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
> -		amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
> -				  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
> -				  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
> -				  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
> -				  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
> -				  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
> -				  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
> -				  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
> -				  PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
> -				  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
> -		amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
> -		amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
> -		amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
> -		amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
> -		amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
> -	}
> -
> -	r = amdgpu_ring_test_helper(kiq_ring);
> -	if (r)
> -		DRM_ERROR("KCQ enable failed\n");
> -
> -	return r;
> -}
> -
>   static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
> @@ -3726,7 +3658,7 @@ static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
>   			goto done;
>   	}
>   
> -	r = gfx_v9_0_kiq_kcq_enable(adev);
> +	r = amdgpu_gfx_enable_kcq(adev);
>   done:
>   	return r;
>   }