[PATCH 3/3] drm/amdgpu: reading register using RREG32_KIQ macro

[Gong, Curry]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex:
Thank you for your comments.
'convert the amdgpu_asic_read_register() callbacks to use KIQ' is a good suggestion. It is something to look at in the future.

BR
Curry Gong

-----Original Message-----
From: Alex Deucher <alexdeucher at gmail.com> 
Sent: Tuesday, January 14, 2020 10:40 PM
To: Gong, Curry <Curry.Gong at amd.com>
Cc: amd-gfx list <amd-gfx at lists.freedesktop.org>
Subject: Re: [PATCH 3/3] drm/amdgpu: reading register using RREG32_KIQ macro

(On Tue, Jan 14, 2020 at 6:42 AM chen gong <curry.gong at amd.com> wrote:
>
> Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to 
> hang when GPU is in "gfxoff" state.
> I do a uniform substitution here.
>
> Signed-off-by: chen gong <curry.gong at amd.com>

Alternatively, we could wrap this function with amdgpu_gfx_off_ctrl() like we do for the AMDGPU_INFO_READ_MMR_REG.  Maybe it would be better to convert the amdgpu_asic_read_register() callbacks to use KIQ as well?  That can be something to look at in the future.

Alex


> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 425762a..cdafacc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4714,12 +4714,12 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
>                 *flags = 0;
>
>         /* AMD_CG_SUPPORT_GFX_MGCG */
> -       data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
> +       data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, 
> + mmRLC_CGTT_MGCG_OVERRIDE));
>         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
>                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
>
>         /* AMD_CG_SUPPORT_GFX_CGCG */
> -       data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
> +       data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, 
> + mmRLC_CGCG_CGLS_CTRL));
>         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
>                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
>
> @@ -4728,18 +4728,18 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
>                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
>
>         /* AMD_CG_SUPPORT_GFX_RLC_LS */
> -       data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
> +       data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, 
> + mmRLC_MEM_SLP_CNTL));
>         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
>                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | 
> AMD_CG_SUPPORT_GFX_MGLS;
>
>         /* AMD_CG_SUPPORT_GFX_CP_LS */
> -       data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
> +       data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
>         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
>                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | 
> AMD_CG_SUPPORT_GFX_MGLS;
>
>         if (adev->asic_type != CHIP_ARCTURUS) {
>                 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
> -               data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
> +               data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, 
> + mmRLC_CGCG_CGLS_CTRL_3D));
>                 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
>                         *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
>
> --
> 2.7.4
>
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