[PATCH v2] drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for Arcturus

[Felix Kuehling]

On 2020-01-24 6:45 p.m., Joseph Greathouse wrote:
> In previous gfx9 parts, S_BARRIER shader instructions are implicitly
> S_WAITCNT 0 instructions as well. This setting turns off that
> mechanism in Arcturus and beyond. With this, shaders must follow
> the ISA guide insofar as putting in explicit S_WAITCNT operations
> even after an S_BARRIER.
>
> v2: Fix patch title to list component
>
> Change-Id: I4f80d6bc0c795b62e1f71bbd09d063b7f75249fd
> Signed-off-by: Joseph Greathouse <Joseph.Greathouse at amd.com>

Reviewed-by: Felix Kuehling <Felix.Kuehling at amd.com>


> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c           | 17 +++++++++++++++++
>   .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h    |  6 ++++--
>   2 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 67ea6a9e13d9..ddde19f9d601 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2441,6 +2441,22 @@ static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
>   	}
>   }
>   
> +static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev)
> +{
> +	uint32_t tmp;
> +
> +	switch (adev->asic_type) {
> +	case CHIP_ARCTURUS:
> +		tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);
> +		tmp = REG_SET_FIELD(tmp, SQ_CONFIG,
> +					DISABLE_BARRIER_WAITCNT, 1);
> +		WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp);
> +		break;
> +	default:
> +		break;
> +	};
> +}
> +
>   static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
>   {
>   	u32 tmp;
> @@ -2486,6 +2502,7 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
>   
>   	gfx_v9_0_init_compute_vmid(adev);
>   	gfx_v9_0_init_gds_vmid(adev);
> +	gfx_v9_0_init_sq_config(adev);
>   }
>   
>   static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
> index c9e3f6d849a8..ea316d8dcb37 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
> @@ -2060,7 +2060,8 @@
>   
>   // addressBlock: gc_sqdec
>   //SQ_CONFIG
> -#define SQ_CONFIG__UNUSED__SHIFT                                                                              0x0
> +#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT__SHIFT                                                             0x0
> +#define SQ_CONFIG__UNUSED__SHIFT                                                                              0x1
>   #define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT                                                                   0x7
>   #define SQ_CONFIG__DEBUG_EN__SHIFT                                                                            0x8
>   #define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT                                                                  0x9
> @@ -2079,7 +2080,8 @@
>   #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT                                                  0x1d
>   #define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT                                                            0x1e
>   #define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT                                                            0x1f
> -#define SQ_CONFIG__UNUSED_MASK                                                                                0x0000007FL
> +#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT_MASK                                                               0x00000001L
> +#define SQ_CONFIG__UNUSED_MASK                                                                                0x0000007EL
>   #define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK                                                                     0x00000080L
>   #define SQ_CONFIG__DEBUG_EN_MASK                                                                              0x00000100L
>   #define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK                                                                    0x00000200L