[PATCH 1/2] drm/amdgpu/display: handle multiple numbers of fclks in dcn_calcs.c
Kazlauskas, Nicholas
nicholas.kazlauskas at amd.com
Wed Jan 29 13:53:29 UTC 2020
On 2020-01-28 2:47 p.m., Alex Deucher wrote:
> We might get different numbers of clocks from powerplay depending
> on what the OEM has populated.
>
> Bug: https://gitlab.freedesktop.org/drm/amd/issues/963
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 31 ++++++++++++-------
> 1 file changed, 20 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> index a27d84ca15a5..8ad32a11d363 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> @@ -1446,17 +1446,26 @@ void dcn_bw_update_from_pplib(struct dc *dc)
> res = verify_clock_values(&fclks);
>
> if (res) {
> - ASSERT(fclks.num_levels >= 3);
> - dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0;
> - dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *
> - (fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0)
> - * ddr4_dram_factor_single_Channel / 1000.0;
> - dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels *
> - (fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0)
> - * ddr4_dram_factor_single_Channel / 1000.0;
> - dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels *
> - (fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0)
> - * ddr4_dram_factor_single_Channel / 1000.0;
> + unsigned vmin0p65_idx = 0;
> + unsigned vmid0p72_idx = fclks.num_levels -
> + (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1));
> + unsigned vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1);
> + unsigned vmax0p9_idx = fclks.num_levels - 1;
Might want an assertion for fclks.num_levels > 0 still, since that's
what the function is expecting now.
With that change, this is:
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>
> +
> + dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 =
> + 32 * (fclks.data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0;
> + dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 =
> + dc->dcn_soc->number_of_channels *
> + (fclks.data[vmid0p72_idx].clocks_in_khz / 1000.0)
> + * ddr4_dram_factor_single_Channel / 1000.0;
> + dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 =
> + dc->dcn_soc->number_of_channels *
> + (fclks.data[vnom0p8_idx].clocks_in_khz / 1000.0)
> + * ddr4_dram_factor_single_Channel / 1000.0;
> + dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 =
> + dc->dcn_soc->number_of_channels *
> + (fclks.data[vmax0p9_idx].clocks_in_khz / 1000.0)
> + * ddr4_dram_factor_single_Channel / 1000.0;
> } else
> BREAK_TO_DEBUGGER();
>
>
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