[PATCH 01/14] drm/amd/powerplay: add more members for dpm table
Alex Deucher
alexdeucher at gmail.com
Thu Jul 9 20:39:17 UTC 2020
On Fri, Jul 3, 2020 at 4:33 AM Evan Quan <evan.quan at amd.com> wrote:
>
> These members can help to cache the clock frequencies for all
> dpm levels. Then simplifying the code for dpm level switching
> is possible.
>
> Change-Id: Ic80359adb8c0e018f306782f24e3f8906436f5e2
> Signed-off-by: Evan Quan <evan.quan at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> index 3d746b75396e..289c571d6e4e 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> @@ -48,6 +48,7 @@
>
> #define SMU11_TOOL_SIZE 0x19000
>
> +#define MAX_DPM_LEVELS 16
> #define MAX_PCIE_CONF 2
>
> #define CLK_MAP(clk, index) \
> @@ -91,9 +92,17 @@ struct smu_11_0_max_sustainable_clocks {
> uint32_t soc_clock;
> };
>
> +struct smu_11_0_dpm_clk_level {
> + bool enabled;
> + uint32_t value;
> +};
> +
> struct smu_11_0_dpm_table {
> - uint32_t min; /* MHz */
> - uint32_t max; /* MHz */
> + uint32_t min; /* MHz */
> + uint32_t max; /* MHz */
> + uint32_t count;
> + bool is_fine_grained;
> + struct smu_11_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS];
> };
>
> struct smu_11_0_pcie_table {
> @@ -107,7 +116,9 @@ struct smu_11_0_dpm_tables {
> struct smu_11_0_dpm_table uclk_table;
> struct smu_11_0_dpm_table eclk_table;
> struct smu_11_0_dpm_table vclk_table;
> + struct smu_11_0_dpm_table vclk1_table;
> struct smu_11_0_dpm_table dclk_table;
> + struct smu_11_0_dpm_table dclk1_table;
> struct smu_11_0_dpm_table dcef_table;
> struct smu_11_0_dpm_table pixel_table;
> struct smu_11_0_dpm_table display_table;
> --
> 2.27.0
>
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