[PATCH 12/16] drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range
Alex Deucher
alexdeucher at gmail.com
Mon Jul 13 14:53:20 UTC 2020
On Fri, Jul 10, 2020 at 12:48 AM Evan Quan <evan.quan at amd.com> wrote:
>
> Use the common smu_v11_0_set_soft_freq_limited_range.
>
> Change-Id: I9f8772880b324ce9e741291751bb1b8ff4c36ea3
> Signed-off-by: Evan Quan <evan.quan at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> .../drm/amd/powerplay/sienna_cichlid_ppt.c | 20 ++-----------------
> drivers/gpu/drm/amd/powerplay/smu_internal.h | 1 -
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 20 +++++++++++++++----
> 3 files changed, 18 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> index 27f77bde184f..141944df97b0 100644
> --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> @@ -1046,22 +1046,6 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
> return size;
> }
>
> -int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
> - enum smu_clk_type clk_type,
> - uint32_t min, uint32_t max)
> -{
> - struct amdgpu_device *adev = smu->adev;
> - int ret;
> -
> - if (clk_type == SMU_GFXCLK)
> - amdgpu_gfx_off_ctrl(adev, false);
> - ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min, max);
> - if (clk_type == SMU_GFXCLK)
> - amdgpu_gfx_off_ctrl(adev, true);
> -
> - return ret;
> -}
> -
> static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
> enum smu_clk_type clk_type, uint32_t mask)
> {
> @@ -1097,7 +1081,7 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
> if (ret)
> goto forec_level_out;
>
> - ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
> + ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
> if (ret)
> goto forec_level_out;
> break;
> @@ -2566,7 +2550,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
> .baco_enter = smu_v11_0_baco_enter,
> .baco_exit = smu_v11_0_baco_exit,
> .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
> - .set_soft_freq_limited_range = sienna_cichlid_set_soft_freq_limited_range,
> + .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
> .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
> .set_thermal_range = sienna_cichlid_set_thermal_range,
> };
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> index 1c808ffe3ab1..91d3965bbe80 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
> +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> @@ -93,7 +93,6 @@
> #define smu_asic_set_performance_level(smu, level) smu_ppt_funcs(set_performance_level, -EINVAL, smu, level)
> #define smu_dump_pptable(smu) smu_ppt_funcs(dump_pptable, 0, smu)
> #define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) smu_ppt_funcs(get_dpm_clk_limited, -EINVAL, smu, clk_type, dpm_level, freq)
> -#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) smu_ppt_funcs(set_soft_freq_limited_range, -EINVAL, smu, clk_type, min, max)
> #define smu_override_pcie_parameters(smu) smu_ppt_funcs(override_pcie_parameters, 0, smu)
> #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap)
> #define smu_set_thermal_range(smu, range) smu_ppt_funcs(set_thermal_range, 0, smu, range)
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index f96ff062eb64..c2779d0b51f6 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1745,9 +1745,12 @@ int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type c
> return ret;
> }
>
> -int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
> - uint32_t min, uint32_t max)
> +int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
> + enum smu_clk_type clk_type,
> + uint32_t min,
> + uint32_t max)
> {
> + struct amdgpu_device *adev = smu->adev;
> int ret = 0, clk_id = 0;
> uint32_t param;
>
> @@ -1755,12 +1758,16 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
> if (clk_id < 0)
> return clk_id;
>
> + if (clk_type == SMU_GFXCLK &&
> + adev->asic_type == CHIP_SIENNA_CICHLID)
> + amdgpu_gfx_off_ctrl(adev, false);
> +
> if (max > 0) {
> param = (uint32_t)((clk_id << 16) | (max & 0xffff));
> ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
> param, NULL);
> if (ret)
> - return ret;
> + goto out;
> }
>
> if (min > 0) {
> @@ -1768,9 +1775,14 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
> ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
> param, NULL);
> if (ret)
> - return ret;
> + goto out;
> }
>
> +out:
> + if (clk_type == SMU_GFXCLK &&
> + adev->asic_type == CHIP_SIENNA_CICHLID)
> + amdgpu_gfx_off_ctrl(adev, true);
> +
> return ret;
> }
>
> --
> 2.27.0
>
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