[PATCH 17/17] drm/amd/powerplay: tag swSMU code layers
Evan Quan
evan.quan at amd.com
Tue Jul 14 08:04:16 UTC 2020
Per designs, the swSMU code is separated into four layers. And the typical
calling flow should be like: amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c
-> smu_cmn.c. Compile errors will come out for any violations. This can
help to prevent cross callings(e.g. amdgpu_smu.c -> ${asic}_ppt.c ->
amdgpu_smu.c -> ${asic}_ppt.c) which were common in our code.
Change-Id: I70e717f4527c736d6263680c69eeda96d1cf9bb6
Signed-off-by: Evan Quan <evan.quan at amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++--
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 ++-
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 ++
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 3 +++
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 3 +++
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 ++-
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 3 ++-
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 3 ++-
drivers/gpu/drm/amd/powerplay/smu_cmn.c | 3 ++-
drivers/gpu/drm/amd/powerplay/smu_cmn.h | 2 ++
drivers/gpu/drm/amd/powerplay/smu_internal.h | 3 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 2 +-
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 ++-
13 files changed, 28 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index ebf8928660b8..f246589cbf30 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -20,14 +20,14 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#define SWSMU_CODE_LAYER_L1
+
#include <linux/firmware.h>
#include <linux/pci.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
#include "smu_internal.h"
-#include "smu_v11_0.h"
-#include "smu_v12_0.h"
#include "atom.h"
#include "arcturus_ppt.h"
#include "navi10_ppt.h"
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 59859eb4796f..fde6a8242565 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -21,10 +21,11 @@
*
*/
+#define SWSMU_CODE_LAYER_L2
+
#include <linux/firmware.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
-#include "smu_internal.h"
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "smu_v11_0.h"
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 05bd6c0d6d7c..812068ba1dd6 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -650,6 +650,7 @@ enum smu_cmn2asic_mapping_type {
#define WORKLOAD_MAP(profile, workload) \
[profile] = {1, (workload)}
+#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
int smu_load_microcode(struct smu_context *smu);
int smu_check_fw_status(struct smu_context *smu);
@@ -783,3 +784,4 @@ int smu_get_dpm_clock_table(struct smu_context *smu,
struct dpm_clocks *clock_table);
#endif
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index e9a3bd294876..6a3ef497c7fd 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -133,6 +133,8 @@ enum smu_v11_0_baco_seq {
BACO_SEQ_COUNT,
};
+#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
+
int smu_v11_0_init_microcode(struct smu_context *smu);
void smu_v11_0_fini_microcode(struct smu_context *smu);
@@ -264,3 +266,4 @@ int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
uint32_t *max_value);
#endif
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
index 52cdd6a0f99a..02de3b6199e5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -31,6 +31,8 @@
#define MP1_Public 0x03b00000
#define MP1_SRAM 0x03c00004
+#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
+
int smu_v12_0_check_fw_status(struct smu_context *smu);
int smu_v12_0_check_fw_version(struct smu_context *smu);
@@ -59,3 +61,4 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
int smu_v12_0_set_driver_table_location(struct smu_context *smu);
#endif
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 9ed2377ababa..edabf4730655 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -21,11 +21,12 @@
*
*/
+#define SWSMU_CODE_LAYER_L2
+
#include <linux/firmware.h>
#include <linux/pci.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
-#include "smu_internal.h"
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "soc15_common.h"
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index fdf27bb90777..fc58adfff0ba 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -21,9 +21,10 @@
*
*/
+#define SWSMU_CODE_LAYER_L2
+
#include "amdgpu.h"
#include "amdgpu_smu.h"
-#include "smu_internal.h"
#include "smu_v12_0_ppsmc.h"
#include "smu12_driver_if.h"
#include "smu_v12_0.h"
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index ace46022cf0d..771a666868a1 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -21,11 +21,12 @@
*
*/
+#define SWSMU_CODE_LAYER_L2
+
#include <linux/firmware.h>
#include <linux/pci.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
-#include "smu_internal.h"
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "smu_v11_0.h"
diff --git a/drivers/gpu/drm/amd/powerplay/smu_cmn.c b/drivers/gpu/drm/amd/powerplay/smu_cmn.c
index 4084c707c04a..be4b678d0e60 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_cmn.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_cmn.c
@@ -20,10 +20,11 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#define SWSMU_CODE_LAYER_L4
+
#include "amdgpu.h"
#include "amdgpu_smu.h"
#include "smu_cmn.h"
-#include "smu_internal.h"
#include "soc15_common.h"
/*
diff --git a/drivers/gpu/drm/amd/powerplay/smu_cmn.h b/drivers/gpu/drm/amd/powerplay/smu_cmn.h
index e07ff6330c54..98face8c5fd6 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_cmn.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_cmn.h
@@ -25,6 +25,7 @@
#include "amdgpu_smu.h"
+#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
enum smu_message_type msg,
uint32_t param,
@@ -79,3 +80,4 @@ int smu_cmn_write_watermarks_table(struct smu_context *smu);
int smu_cmn_write_pptable(struct smu_context *smu);
#endif
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index e221bd2c466a..58a4cbafcfb2 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -25,6 +25,8 @@
#include "amdgpu_smu.h"
+#if defined(SWSMU_CODE_LAYER_L1)
+
#define smu_ppt_funcs(intf, ret, smu, args...) \
((smu)->ppt_funcs ? ((smu)->ppt_funcs->intf ? (smu)->ppt_funcs->intf(smu, ##args) : ret) : -EINVAL)
@@ -94,3 +96,4 @@
#define smu_set_pp_feature_mask(smu, new_mask) smu_ppt_funcs(set_pp_feature_mask, 0, smu, new_mask)
#endif
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index dd45f271d2be..69762f94936e 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -26,10 +26,10 @@
#include <linux/reboot.h>
#define SMU_11_0_PARTIAL_PPTABLE
+#define SWSMU_CODE_LAYER_L3
#include "amdgpu.h"
#include "amdgpu_smu.h"
-#include "smu_internal.h"
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "smu_v11_0.h"
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 7855e8d88af7..31456437bb18 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -20,10 +20,11 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#define SWSMU_CODE_LAYER_L3
+
#include <linux/firmware.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
-#include "smu_internal.h"
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "smu_v12_0.h"
--
2.27.0
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