[PATCH 2/5] drm/amdgpu: optimize rlcg write for gfx_v10

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

Acked-by: Alex Deucher <alexander.deucher at amd.com>
________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Jack Zhang <Jack.Zhang1 at amd.com>
Sent: Monday, July 13, 2020 10:46 PM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Zhang, Jack (Jian) <Jack.Zhang1 at amd.com>; Liu, Leo <Leo.Liu at amd.com>; Zhang, Hawking <Hawking.Zhang at amd.com>
Subject: [PATCH 2/5] drm/amdgpu: optimize rlcg write for gfx_v10

For gfx10 boards, except for nv12, other boards take mmio write
rather than rlcg write
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +++++++++++++++++++-------
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index c1f8c986380c..a78a6a1b593a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4728,12 +4728,19 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);

         /* csib */
-       WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
-                        adev->gfx.rlc.clear_state_gpu_addr >> 32);
-       WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
-                        adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
-       WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
-
+       if (adev->asic_type == CHIP_NAVI12) {
+               WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
+                               adev->gfx.rlc.clear_state_gpu_addr >> 32);
+               WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
+                               adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
+               WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
+       } else {
+               WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
+                               adev->gfx.rlc.clear_state_gpu_addr >> 32);
+               WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
+                               adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
+               WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
+       }
         return 0;
 }

@@ -5341,7 +5348,12 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
-       WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
+
+       if (adev->asic_type == CHIP_NAVI12) {
+               WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
+       } else {
+               WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
+       }

         for (i = 0; i < adev->usec_timeout; i++) {
                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
--
2.17.1

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