[PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs

[Deucher, Alexander]

[AMD Public Use]

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
________________________________
From: Quan, Evan <Evan.Quan at amd.com>
Sent: Tuesday, July 14, 2020 2:55 AM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: RE: [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,

Can I have a RB for this patch also?

BR
Evan
-----Original Message-----
From: Quan, Evan
Sent: Monday, July 13, 2020 11:45 AM
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: RE: [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs

Ping for this one and patch12, patch2 and patch3

BR
Evan
-----Original Message-----
From: Quan, Evan <Evan.Quan at amd.com>
Sent: Friday, July 10, 2020 12:48 PM
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Quan, Evan <Evan.Quan at amd.com>
Subject: [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs

Before and after setting gfx clock soft max/min frequency.

Change-Id: I6f828da8de096ebc0ae27eaa89f988def2d547ec
Signed-off-by: Evan Quan <evan.quan at amd.com>
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index c2779d0b51f6..33e0718f2635 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1758,8 +1758,7 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
 if (clk_id < 0)
 return clk_id;

-if (clk_type == SMU_GFXCLK &&
-    adev->asic_type == CHIP_SIENNA_CICHLID)
+if (clk_type == SMU_GFXCLK)
 amdgpu_gfx_off_ctrl(adev, false);

 if (max > 0) {
@@ -1779,8 +1778,7 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
 }

 out:
-if (clk_type == SMU_GFXCLK &&
-    adev->asic_type == CHIP_SIENNA_CICHLID)
+if (clk_type == SMU_GFXCLK)
 amdgpu_gfx_off_ctrl(adev, true);

 return ret;
--
2.27.0

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