[PATCH 05/16] drm/amd/powerplay: clean up the APIs for bootup clocks
Evan Quan
evan.quan at amd.com
Thu Jun 4 04:46:08 UTC 2020
Combine and simplify the logics for retrieving bootup
clocks.
Change-Id: Ifca28c454f3769dece0cc705ba054ff34db0ab60
Signed-off-by: Evan Quan <evan.quan at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 -
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 1 -
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 -
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 -
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1 -
.../drm/amd/powerplay/sienna_cichlid_ppt.c | 1 -
drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 -
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 141 +++++++-----------
8 files changed, 51 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 0e459186a2bf..b2dad4d09d88 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1114,10 +1114,6 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
if (ret)
return ret;
- ret = smu_get_clk_info_from_vbios(smu);
- if (ret)
- return ret;
-
/*
* check if the format_revision in vbios is up to pptable header
* version, and the structure size is not 0.
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 1de5304d12bf..747fdd315575 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -2457,7 +2457,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.check_fw_status = smu_v11_0_check_fw_status,
.setup_pptable = smu_v11_0_setup_pptable,
.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
- .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
.check_pptable = smu_v11_0_check_pptable,
.parse_pptable = smu_v11_0_parse_pptable,
.populate_smc_tables = smu_v11_0_populate_smc_pptable,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 210432187ceb..cab64f896c4b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -506,7 +506,6 @@ struct pptable_funcs {
int (*check_fw_status)(struct smu_context *smu);
int (*setup_pptable)(struct smu_context *smu);
int (*get_vbios_bootup_values)(struct smu_context *smu);
- int (*get_clk_info_from_vbios)(struct smu_context *smu);
int (*check_pptable)(struct smu_context *smu);
int (*parse_pptable)(struct smu_context *smu);
int (*populate_smc_tables)(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 4682a2fd4381..79736b1e3506 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -162,8 +162,6 @@ int smu_v11_0_setup_pptable(struct smu_context *smu);
int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
-int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu);
-
int smu_v11_0_check_pptable(struct smu_context *smu);
int smu_v11_0_parse_pptable(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index a43c16befffd..85c7cceef9dc 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -2319,7 +2319,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.check_fw_status = smu_v11_0_check_fw_status,
.setup_pptable = smu_v11_0_setup_pptable,
.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
- .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
.check_pptable = smu_v11_0_check_pptable,
.parse_pptable = smu_v11_0_parse_pptable,
.populate_smc_tables = smu_v11_0_populate_smc_pptable,
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index f83df6adcbce..3405bdcbfbd9 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -2457,7 +2457,6 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.check_fw_status = smu_v11_0_check_fw_status,
.setup_pptable = smu_v11_0_setup_pptable,
.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
- .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
.check_pptable = smu_v11_0_check_pptable,
.parse_pptable = smu_v11_0_parse_pptable,
.populate_smc_tables = smu_v11_0_populate_smc_pptable,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index c9440c978402..496a401615c6 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -47,8 +47,6 @@
#define smu_get_vbios_bootup_values(smu) \
((smu)->ppt_funcs->get_vbios_bootup_values ? (smu)->ppt_funcs->get_vbios_bootup_values((smu)) : 0)
-#define smu_get_clk_info_from_vbios(smu) \
- ((smu)->ppt_funcs->get_clk_info_from_vbios ? (smu)->ppt_funcs->get_clk_info_from_vbios((smu)) : 0)
#define smu_check_pptable(smu) \
((smu)->ppt_funcs->check_pptable ? (smu)->ppt_funcs->check_pptable((smu)) : 0)
#define smu_parse_pptable(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 45d4fd2526eb..ef825327974c 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -565,6 +565,32 @@ int smu_v11_0_fini_power(struct smu_context *smu)
return 0;
}
+static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
+ uint8_t clk_id,
+ uint8_t syspll_id,
+ uint32_t *clk_freq)
+{
+ struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
+ struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
+ int ret, index;
+
+ input.clk_id = clk_id;
+ input.syspll_id = syspll_id;
+ input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+ index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+ getsmuclockinfo);
+
+ ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
+ (uint32_t *)&input);
+ if (ret)
+ return -EINVAL;
+
+ output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+ *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+
+ return 0;
+}
+
int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
{
int ret, index;
@@ -623,102 +649,37 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
smu->smu_table.boot_values.format_revision = header->format_revision;
smu->smu_table.boot_values.content_revision = header->content_revision;
- return 0;
-}
+ smu_v11_0_atom_get_smu_clockinfo(smu->adev,
+ (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
+ (uint8_t)0,
+ &smu->smu_table.boot_values.socclk);
-int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
-{
- int ret, index;
- struct amdgpu_device *adev = smu->adev;
- struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
- struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
+ smu_v11_0_atom_get_smu_clockinfo(smu->adev,
+ (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
+ (uint8_t)0,
+ &smu->smu_table.boot_values.dcefclk);
- input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
- input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
- index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
- getsmuclockinfo);
-
- ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
- (uint32_t *)&input);
- if (ret)
- return -EINVAL;
+ smu_v11_0_atom_get_smu_clockinfo(smu->adev,
+ (uint8_t)SMU11_SYSPLL0_ECLK_ID,
+ (uint8_t)0,
+ &smu->smu_table.boot_values.eclk);
- output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
- smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+ smu_v11_0_atom_get_smu_clockinfo(smu->adev,
+ (uint8_t)SMU11_SYSPLL0_VCLK_ID,
+ (uint8_t)0,
+ &smu->smu_table.boot_values.vclk);
- memset(&input, 0, sizeof(input));
- input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
- input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
- index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
- getsmuclockinfo);
-
- ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
- (uint32_t *)&input);
- if (ret)
- return -EINVAL;
-
- output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
- smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
-
- memset(&input, 0, sizeof(input));
- input.clk_id = SMU11_SYSPLL0_ECLK_ID;
- input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
- index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
- getsmuclockinfo);
-
- ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
- (uint32_t *)&input);
- if (ret)
- return -EINVAL;
-
- output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
- smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
-
- memset(&input, 0, sizeof(input));
- input.clk_id = SMU11_SYSPLL0_VCLK_ID;
- input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
- index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
- getsmuclockinfo);
-
- ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
- (uint32_t *)&input);
- if (ret)
- return -EINVAL;
-
- output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
- smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
-
- memset(&input, 0, sizeof(input));
- input.clk_id = SMU11_SYSPLL0_DCLK_ID;
- input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
- index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
- getsmuclockinfo);
-
- ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
- (uint32_t *)&input);
- if (ret)
- return -EINVAL;
-
- output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
- smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+ smu_v11_0_atom_get_smu_clockinfo(smu->adev,
+ (uint8_t)SMU11_SYSPLL0_DCLK_ID,
+ (uint8_t)0,
+ &smu->smu_table.boot_values.dclk);
if ((smu->smu_table.boot_values.format_revision == 3) &&
- (smu->smu_table.boot_values.content_revision >= 2)) {
- memset(&input, 0, sizeof(input));
- input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
- input.syspll_id = SMU11_SYSPLL1_2_ID;
- input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
- index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
- getsmuclockinfo);
-
- ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
- (uint32_t *)&input);
- if (ret)
- return -EINVAL;
-
- output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
- smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
- }
+ (smu->smu_table.boot_values.content_revision >= 2))
+ smu_v11_0_atom_get_smu_clockinfo(smu->adev,
+ (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
+ (uint8_t)SMU11_SYSPLL1_2_ID,
+ &smu->smu_table.boot_values.fclk);
return 0;
}
--
2.27.0
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