[PATCH] drm/amdgpu: fix the nullptr issue as for PWR IP not existing in discovery table

[Nirmoy]

On 6/5/20 1:34 PM, Prike.Liang wrote:
> fix e467ab869f57 drm/amdgpu: use IP discovery table for renoir.
>
> This nullptr issue should be specific on the Renoir series during try access the PWR_MISC_CNTL_STATUS
> when PWR IP not been detected by discovery table. Moreover the PWR IP not existing in Renoir series is
> expected therefore just avoid access PWR register in Renoir series.
>
> Signed-off-by: Prike.Liang <Prike.Liang at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 22943773..6b94587 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2856,8 +2856,8 @@ static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
>   		/* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
>   		data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
>   		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
> -
> -		pwr_10_0_gfxip_control_over_cgpg(adev, true);
> +		if (adev->asic_type != CHIP_RENOIR)


You should move that check inside pwr_10_0_gfxip_control_over_cgpg() for 
better understanding.

Otherwise Acked-by: Nirmoy Das <nirmoy.das at amd.com>


Nirmoy

> +			pwr_10_0_gfxip_control_over_cgpg(adev, true);
>   	}
>   }
>