[PATCH 18/28] drm/amd/display: add support for per-state dummy-pstate latency

Qingqing Zhuo qingqing.zhuo at amd.com
Mon Jun 8 04:59:16 UTC 2020

From: Jun Lei <jun.lei at amd.com>

Dummy pstate latency actually varies between different
UCLK frequencies, when calculating watermark C, if DAL
always assumes worst case, then it can lead to dummy
pstate not supported scenarios.

Rather than statically calculating dummy pstate using
worst case, we store the entire table of UCLK to dummy
pstate relationships.  On a per mode basis, we calculate
the actual UCLK lower limit, and use the dynamic worst
case dummy pstate latency.  This prevents the situation
where we don't support full p-state (which will force
high DPM), but still use low DPM dummy pstate latency.

Signed-off-by: Jun Lei <jun.lei at amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback at amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo at amd.com>
 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 49c50af9cd9e..505357597603 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -198,11 +198,17 @@ struct wm_table {
+struct dummy_pstate_entry {
+	unsigned int dram_speed_mts;
+	unsigned int dummy_pstate_latency_us;
 struct clk_bw_params {
 	unsigned int vram_type;
 	unsigned int num_channels;
 	struct clk_limit_table clk_table;
 	struct wm_table wm_table;
+	struct dummy_pstate_entry dummy_pstate_table[4];
 /* Public interfaces */

More information about the amd-gfx mailing list