[PATCH] drm/amd/amdgpu: Add SQ debug registers to GFX10 headers
Deucher, Alexander
Alexander.Deucher at amd.com
Tue Jun 9 18:14:11 UTC 2020
[AMD Official Use Only - Internal Distribution Only]
Might as well add it for gfx9 as well. With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Tom St Denis <tom.stdenis at amd.com>
Sent: Tuesday, June 9, 2020 1:59 PM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: StDenis, Tom <Tom.StDenis at amd.com>
Subject: [PATCH] drm/amd/amdgpu: Add SQ debug registers to GFX10 headers
Requested for UMR support.
Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
---
.../include/asic_reg/gc/gc_10_1_0_offset.h | 1 +
.../include/asic_reg/gc/gc_10_1_0_sh_mask.h | 20 +++++++++++++++++++
.../include/asic_reg/gc/gc_10_3_0_offset.h | 1 +
.../include/asic_reg/gc/gc_10_3_0_sh_mask.h | 19 ++++++++++++++++++
4 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
index 075867d4b1da..791dc2b3d74a 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
@@ -11151,6 +11151,7 @@
// addressBlock: sqind
// base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL 0x0008
#define ixSQ_WAVE_MODE 0x0101
#define ixSQ_WAVE_STATUS 0x0102
#define ixSQ_WAVE_TRAPSTS 0x0103
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
index 8b0b9a2a8fed..355e61bed291 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
@@ -42546,6 +42546,26 @@
// addressBlock: sqind
+//SQ_DEBUG_STS_LOCAL
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK 0x00001000L
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT 0x0000000C
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK 0x00002000L
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT 0x0000000D
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK 0x00004000L
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT 0x0000000E
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK 0x00008000L
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT 0x0000000F
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK 0x00010000L
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT 0x00000010
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK 0x00020000L
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT 0x00000011
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK 0x00040000L
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT 0x00000018
+
//SQ_WAVE_MODE
#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
index 71c787d66132..a9a66371b75e 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
@@ -13277,6 +13277,7 @@
// addressBlock: sqind
// base address: 0x0
+#define ixSQ_DEBUG_STS_LOCAL 0x0008
#define ixSQ_WAVE_ACTIVE 0x000a
#define ixSQ_WAVE_VALID_AND_IDLE 0x000b
#define ixSQ_WAVE_MODE 0x0101
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
index 00bae8e09f84..499a8c3c2693 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
@@ -46269,6 +46269,25 @@
// addressBlock: sqind
+//SQ_DEBUG_STS_LOCAL
+#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L
+#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L
+#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK 0x00001000L
+#define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT 0x0000000C
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK 0x00002000L
+#define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT 0x0000000D
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK 0x00004000L
+#define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT 0x0000000E
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK 0x00008000L
+#define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT 0x0000000F
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK 0x00010000L
+#define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT 0x00000010
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK 0x00020000L
+#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT 0x00000011
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK 0x00040000L
+#define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT 0x00000018
//SQ_WAVE_ACTIVE
#define SQ_WAVE_ACTIVE__WAVE_SLOT__SHIFT 0x0
#define SQ_WAVE_ACTIVE__WAVE_SLOT_MASK 0x000FFFFFL
--
2.26.2
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