[PATCH] drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)

[Alex Deucher]

On Tue, Jun 16, 2020 at 11:26 AM Tom St Denis <tom.stdenis at amd.com> wrote:
>
> Despite having different IP offsets the computed address of the register(s)
> are the same between gfx7..gfx10.  This patch fixes the offset relative
> to the GC block on gfx10.
>
> (v2): SQ_DEBUG_STS_GLOBAL2 is 0x10 higher ...
>
> Signed-off-by: Tom St Denis <tom.stdenis at amd.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>


> ---
>  drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h | 4 ++--
>  drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> index baac40fa70e7..18d34bbceebe 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
> @@ -21,9 +21,9 @@
>  #ifndef _gc_10_1_0_OFFSET_HEADER
>  #define _gc_10_1_0_OFFSET_HEADER
>
> -#define mmSQ_DEBUG_STS_GLOBAL                                                                          0x0309
> +#define mmSQ_DEBUG_STS_GLOBAL                                                                          0x10A9
>  #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX                                                                 0
> -#define mmSQ_DEBUG_STS_GLOBAL2                                                                         0x0310
> +#define mmSQ_DEBUG_STS_GLOBAL2                                                                         0x10B0
>  #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX                                                                0
>
>  // addressBlock: gc_sdma0_sdma0dec
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
> index 0bde3b4e9567..05d1b0a5f6d2 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
> @@ -22,9 +22,9 @@
>  #ifndef _gc_10_3_0_OFFSET_HEADER
>  #define _gc_10_3_0_OFFSET_HEADER
>
> -#define mmSQ_DEBUG_STS_GLOBAL                                                                          0x0309
> +#define mmSQ_DEBUG_STS_GLOBAL                                                                          0x10A9
>  #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX                                                                 0
> -#define mmSQ_DEBUG_STS_GLOBAL2                                                                         0x0310
> +#define mmSQ_DEBUG_STS_GLOBAL2                                                                         0x10B0
>  #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX                                                                0
>
>  // addressBlock: gc_sdma0_sdma0dec
> --
> 2.26.2
>
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