[PATCH 06/30] drm/amd/display: implement edid max TMDS clock check in DC
Rodrigo Siqueira
Rodrigo.Siqueira at amd.com
Fri Jun 19 20:11:58 UTC 2020
From: Michael Strauss <michael.strauss at amd.com>
[WHY]
Currently DC doesn't check requested pixel clock against an EDID
specified TMDS max clock if it exists, passing modes that should fail
[HOW]
Add max TMDS clk to edid caps and perform check during validation
Signed-off-by: Michael Strauss <michael.strauss at amd.com>
Reviewed-by: Eric Yang <eric.yang2 at amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 3 +++
.../gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 10 ++++++++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index d7b9d311d9e0..f51e5766d8f5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -261,6 +261,9 @@ struct dc_edid_caps {
bool edid_hdmi;
bool hdr_supported;
+ uint32_t max_tmds_clk_mhz;
+ uint32_t max_forum_tmds_clk_mhz;
+
struct dc_panel_patch panel_patch;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index 7fd385be3f3d..a9af3f6fd8ec 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -619,11 +619,20 @@ bool dcn10_link_encoder_validate_dvi_output(
static bool dcn10_link_encoder_validate_hdmi_output(
const struct dcn10_link_encoder *enc10,
const struct dc_crtc_timing *crtc_timing,
+ const struct dc_edid_caps *edid_caps,
int adjusted_pix_clk_100hz)
{
enum dc_color_depth max_deep_color =
enc10->base.features.max_hdmi_deep_color;
+ // check pixel clock against edid specified max TMDS clk
+ if (edid_caps->max_tmds_clk_mhz != 0 &&
+ adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000)
+ return false;
+ if (edid_caps->max_forum_tmds_clk_mhz != 0 &&
+ adjusted_pix_clk_100hz > edid_caps->max_forum_tmds_clk_mhz * 10000)
+ return false;
+
if (max_deep_color < crtc_timing->display_color_depth)
return false;
@@ -801,6 +810,7 @@ bool dcn10_link_encoder_validate_output_with_stream(
is_valid = dcn10_link_encoder_validate_hdmi_output(
enc10,
&stream->timing,
+ &stream->sink->edid_caps,
stream->phy_pix_clk * 10);
break;
case SIGNAL_TYPE_DISPLAY_PORT:
--
2.27.0
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