[PATCH 1/2] drm/amdgpu: Clean up KFD VMID assignment
Christian König
ckoenig.leichtzumerken at gmail.com
Thu Jun 25 08:18:50 UTC 2020
Am 25.06.20 um 05:18 schrieb Felix Kuehling:
> The KFD VMID assignment was hard-coded in a few places. Consolidate that in
> a single variable adev->vm_manager.first_kfd_vmid. The value is still
> assigned in gmc-ip-version-specific code.
>
> Signed-off-by: Felix Kuehling <Felix.Kuehling at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com> for this one.
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 12 +++++-------
> drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 3 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 1 +
> drivers/gpu/drm/amd/amdgpu/cikd.h | 2 --
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ++----
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++----
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 ++----
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++----
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 5 +----
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +------
> drivers/gpu/drm/amd/amdgpu/si_enums.h | 1 -
> drivers/gpu/drm/amd/amdgpu/sid.h | 2 --
> drivers/gpu/drm/amd/amdgpu/vid.h | 2 --
> 16 files changed, 22 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index ad59ac4423b8..1b865fed74ca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -31,8 +31,6 @@
> #include "amdgpu_xgmi.h"
> #include <uapi/linux/kfd_ioctl.h>
>
> -static const unsigned int compute_vmid_bitmap = 0xFF00;
> -
> /* Total memory size in system memory and all GPU VRAM. Used to
> * estimate worst case amount of memory to reserve for page tables
> */
> @@ -113,7 +111,9 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
>
> if (adev->kfd.dev) {
> struct kgd2kfd_shared_resources gpu_resources = {
> - .compute_vmid_bitmap = compute_vmid_bitmap,
> + .compute_vmid_bitmap =
> + ((1 << AMDGPU_NUM_VMID) - 1) -
> + ((1 << adev->vm_manager.first_kfd_vmid) - 1),
> .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
> .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
> .gpuvm_size = min(adev->vm_manager.max_pfn
> @@ -637,10 +637,8 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
>
> bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
> {
> - if (adev->kfd.dev) {
> - if ((1 << vmid) & compute_vmid_bitmap)
> - return true;
> - }
> + if (adev->kfd.dev)
> + return vmid >= adev->vm_manager.first_kfd_vmid;
>
> return false;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
> index 267fa45ddb66..7521f4ab55de 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
> @@ -574,6 +574,9 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
> INIT_LIST_HEAD(&id_mgr->ids_lru);
> atomic_set(&id_mgr->reserved_vmid_num, 0);
>
> + /* manage only VMIDs not used by KFD */
> + id_mgr->num_ids = adev->vm_manager.first_kfd_vmid;
> +
> /* skip over VMID 0, since it is the system VM */
> for (j = 1; j < id_mgr->num_ids; ++j) {
> amdgpu_vmid_reset(adev, i, j);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index c8e68d7890bf..770025a5e500 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -324,6 +324,7 @@ struct amdgpu_vm {
> struct amdgpu_vm_manager {
> /* Handling of VMIDs */
> struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
> + unsigned int first_kfd_vmid;
>
> /* Handling of VM fences */
> u64 fence_context;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h
> index 5f3f6ebfb387..55982c0064b5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cikd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/cikd.h
> @@ -54,8 +54,6 @@
> #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
> #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
>
> -#define AMDGPU_NUM_OF_VMIDS 8
> -
> #define PIPEID(x) ((x) << 0)
> #define MEID(x) ((x) << 2)
> #define VMID(x) ((x) << 4)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 323285eb1457..8366c506a8b5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4512,8 +4512,6 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
> }
>
> #define DEFAULT_SH_MEM_BASES (0x6000)
> -#define FIRST_COMPUTE_VMID (8)
> -#define LAST_COMPUTE_VMID (16)
>
> static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
> {
> @@ -4529,7 +4527,7 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
> sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
>
> mutex_lock(&adev->srbm_mutex);
> - for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
> + for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
> nv_grbm_select(adev, 0, 0, 0, i);
> /* CP and shaders */
> WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
> @@ -4540,7 +4538,7 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
>
> /* Initialize all compute VMIDs to have no GDS, GWS, or OA
> acccess. These should be enabled by FW for target VMIDs. */
> - for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
> + for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 4aec76049a60..04eaf3a8fddb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -1850,8 +1850,6 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
> *
> */
> #define DEFAULT_SH_MEM_BASES (0x6000)
> -#define FIRST_COMPUTE_VMID (8)
> -#define LAST_COMPUTE_VMID (16)
> static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
> {
> int i;
> @@ -1869,7 +1867,7 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
> SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
> sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
> mutex_lock(&adev->srbm_mutex);
> - for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
> + for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
> cik_srbm_select(adev, 0, 0, 0, i);
> /* CP and shaders */
> WREG32(mmSH_MEM_CONFIG, sh_mem_config);
> @@ -1882,7 +1880,7 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
>
> /* Initialize all compute VMIDs to have no GDS, GWS, or OA
> acccess. These should be enabled by FW for target VMIDs. */
> - for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
> + for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
> WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
> WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
> WREG32(amdgpu_gds_reg_offset[i].gws, 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index efb759b62d21..33f1c4a46ebe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -3686,8 +3686,6 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
> *
> */
> #define DEFAULT_SH_MEM_BASES (0x6000)
> -#define FIRST_COMPUTE_VMID (8)
> -#define LAST_COMPUTE_VMID (16)
> static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
> {
> int i;
> @@ -3710,7 +3708,7 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
> SH_MEM_CONFIG__PRIVATE_ATC_MASK;
>
> mutex_lock(&adev->srbm_mutex);
> - for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
> + for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
> vi_srbm_select(adev, 0, 0, 0, i);
> /* CP and shaders */
> WREG32(mmSH_MEM_CONFIG, sh_mem_config);
> @@ -3723,7 +3721,7 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
>
> /* Initialize all compute VMIDs to have no GDS, GWS, or OA
> acccess. These should be enabled by FW for target VMIDs. */
> - for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
> + for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
> WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
> WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
> WREG32(amdgpu_gds_reg_offset[i].gws, 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 99ffc3e1fddc..cb9d60a4e05e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2463,8 +2463,6 @@ static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
> }
>
> #define DEFAULT_SH_MEM_BASES (0x6000)
> -#define FIRST_COMPUTE_VMID (8)
> -#define LAST_COMPUTE_VMID (16)
> static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
> {
> int i;
> @@ -2484,7 +2482,7 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
> SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
>
> mutex_lock(&adev->srbm_mutex);
> - for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
> + for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
> soc15_grbm_select(adev, 0, 0, 0, i);
> /* CP and shaders */
> WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
> @@ -2495,7 +2493,7 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
>
> /* Initialize all compute VMIDs to have no GDS, GWS, or OA
> acccess. These should be enabled by FW for target VMIDs. */
> - for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
> + for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
> WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index f7e66bf0f647..bfe62985afff 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -49,8 +49,6 @@
> #include "mmhub_v2_0.h"
> #include "athub_v2_0.h"
> #include "athub_v2_1.h"
> -/* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/
> -#define AMDGPU_NUM_OF_VMIDS 8
>
> #if 0
> static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
> @@ -905,8 +903,7 @@ static int gmc_v10_0_sw_init(void *handle)
> * amdgpu graphics/compute will use VMIDs 1-7
> * amdkfd will use VMIDs 8-15
> */
> - adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
> - adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
> + adev->vm_manager.first_kfd_vmid = 8;
>
> amdgpu_vm_manager_init(adev);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index a75e472b4a81..538e7ee35cdf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -878,7 +878,7 @@ static int gmc_v6_0_sw_init(void *handle)
> * amdgpu graphics/compute will use VMIDs 1-7
> * amdkfd will use VMIDs 8-15
> */
> - adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
> + adev->vm_manager.first_kfd_vmid = 8;
> amdgpu_vm_manager_init(adev);
>
> /* base offset of vram pages */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index bcd4baecfe11..e18296dc1386 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -1052,7 +1052,7 @@ static int gmc_v7_0_sw_init(void *handle)
> * amdgpu graphics/compute will use VMIDs 1-7
> * amdkfd will use VMIDs 8-15
> */
> - adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
> + adev->vm_manager.first_kfd_vmid = 8;
> amdgpu_vm_manager_init(adev);
>
> /* base offset of vram pages */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 26976e50e2a2..a9e722b8a458 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1177,7 +1177,7 @@ static int gmc_v8_0_sw_init(void *handle)
> * amdgpu graphics/compute will use VMIDs 1-7
> * amdkfd will use VMIDs 8-15
> */
> - adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
> + adev->vm_manager.first_kfd_vmid = 8;
> amdgpu_vm_manager_init(adev);
>
> /* base offset of vram pages */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 11e93a82131d..6e10b42c57e5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -68,9 +68,6 @@
> #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
> #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
>
> -/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
> -#define AMDGPU_NUM_OF_VMIDS 8
> -
> static const u32 golden_settings_vega10_hdp[] =
> {
> 0xf64, 0x0fffffff, 0x00000000,
> @@ -1251,9 +1248,7 @@ static int gmc_v9_0_sw_init(void *handle)
> * amdgpu graphics/compute will use VMIDs 1-7
> * amdkfd will use VMIDs 8-15
> */
> - adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
> - adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
> - adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS;
> + adev->vm_manager.first_kfd_vmid = 8;
>
> amdgpu_vm_manager_init(adev);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h
> index 790ba46eaebb..4e935baa7b91 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_enums.h
> +++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h
> @@ -121,7 +121,6 @@
> #define CURSOR_UPDATE_LOCK (1 << 16)
> #define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
>
> -#define AMDGPU_NUM_OF_VMIDS 8
> #define SI_CRTC0_REGISTER_OFFSET 0
> #define SI_CRTC1_REGISTER_OFFSET 0x300
> #define SI_CRTC2_REGISTER_OFFSET 0x2600
> diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h
> index 5f660f0c819f..ca2e9d661b28 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sid.h
> +++ b/drivers/gpu/drm/amd/amdgpu/sid.h
> @@ -48,8 +48,6 @@
> #define SI_MAX_TCC 16
> #define SI_MAX_TCC_MASK 0xFFFF
>
> -#define AMDGPU_NUM_OF_VMIDS 8
> -
> /* SMC IND accessor regs */
> #define SMC_IND_INDEX_0 0x80
> #define SMC_IND_DATA_0 0x81
> diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
> index 7a01e6133798..80ce42aacc0c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vid.h
> +++ b/drivers/gpu/drm/amd/amdgpu/vid.h
> @@ -67,8 +67,6 @@
> #define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898)
> #define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898)
>
> -#define AMDGPU_NUM_OF_VMIDS 8
> -
> #define PIPEID(x) ((x) << 0)
> #define MEID(x) ((x) << 2)
> #define VMID(x) ((x) << 4)
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