[PATCH] drm/amdgpu: Adding wait time before reading upll control register

[Christian König]

Am 26.06.20 um 18:12 schrieb Alex Jivin:
> Adding a delay between writing to UVD control register and reading from it.
> This is to allow the HW to process the write command.
>
> Signed-off-by: Alex Jivin <alex.jivin at amd.com>
> Suggested-By: Luben Tukov <luben.tuikov at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/si.c | 6 ++++++
>   1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
> index 9d7b4ccd17b8..42cdc14fb79d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -1435,6 +1435,12 @@ static int si_uvd_send_upll_ctlreq(struct amdgpu_device *adev,
>   	/* Assert UPLL_CTLREQ */
>   	WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
>   
> +	/* Waiting for HW to process the previous write.
> +	 * This is to give a chance to HW to act before
> +	 * the first read is done.
> +	 */
> +	mdelay(1);
> +

Mhm, that is most likely not a good idea.

We need to issue a read after the write to make sure that the stuff is 
send out to the hardware.

Adding a delay here is probably just postponing that. Do we have some 
note in the documentation that this is necessary?

Christian.

>   	/* Wait for CTLACK and CTLACK2 to get asserted */
>   	for (i = 0; i < SI_MAX_CTLACKS_ASSERTION_WAIT; ++i) {
>   		uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;