[PATCH 2/2] drm/amdgpu/display: Fix Pollock Variant Detection

[Alex Deucher]

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On Tue, Feb 25, 2020 at 3:32 PM Alex Deucher <alexdeucher at gmail.com> wrote:
>
> From: Aly-Tawfik <altawfik at amd.com>
>
> Problem Description:
> Currently we are checking internal fused rev id with pci rev id. However, fused
> internal rev id is the same on all raven2 parts (in which Dali and Pollock were
> based on too), thus Pollock detection fails
>
> Fix:
> use the pci rev to preform the detection for bandwidth calculations.
>
> Signed-off-by: Aly-Tawfik <altawfik at amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
>  drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c |  5 +++++
>  .../gpu/drm/amd/display/include/dal_asic_id.h    | 16 ++++++----------
>  2 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> index f0f07b160152..3960a8db94cb 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> @@ -712,6 +712,11 @@ unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev, uint32_
>                 case PRID_DALI_DF:
>                 case PRID_DALI_E3:
>                 case PRID_DALI_E4:
> +               case PRID_POLLOCK_94:
> +               case PRID_POLLOCK_95:
> +               case PRID_POLLOCK_E9:
> +               case PRID_POLLOCK_EA:
> +               case PRID_POLLOCK_EB:
>                         return 0;
>                 default:
>                         break;
> diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> index ea7015f869c9..8a87d0ed90ae 100644
> --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> @@ -134,11 +134,6 @@
>  #define PICASSO_A0 0x41
>  /* DCN1_01 */
>  #define RAVEN2_A0 0x81
> -#define RAVEN2_15D8_REV_94 0x94
> -#define RAVEN2_15D8_REV_95 0x95
> -#define RAVEN2_15D8_REV_E9 0xE9
> -#define RAVEN2_15D8_REV_EA 0xEA
> -#define RAVEN2_15D8_REV_EB 0xEB
>  #define RAVEN1_F0 0xF0
>  #define RAVEN_UNKNOWN 0xFF
>  #ifndef ASICREV_IS_RAVEN
> @@ -149,16 +144,17 @@
>  #define PRID_DALI_E3 0xE3
>  #define PRID_DALI_E4 0xE4
>
> +#define PRID_POLLOCK_94 0x94
> +#define PRID_POLLOCK_95 0x95
> +#define PRID_POLLOCK_E9 0xE9
> +#define PRID_POLLOCK_EA 0xEA
> +#define PRID_POLLOCK_EB 0xEB
> +
>  #define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
>  #ifndef ASICREV_IS_RAVEN2
>  #define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < RENOIR_A0))
>  #endif
>  #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
> -#define ASICREV_IS_POLLOCK(eChipRev) (eChipRev == RAVEN2_15D8_REV_94 \
> -               || eChipRev == RAVEN2_15D8_REV_95 \
> -                       || eChipRev == RAVEN2_15D8_REV_E9 \
> -                               || eChipRev == RAVEN2_15D8_REV_EA \
> -                                       || eChipRev == RAVEN2_15D8_REV_EB)
>
>  #define FAMILY_RV 142 /* DCN 1*/
>
> --
> 2.24.1
>