[PATCH] drm/amdgpu: update page retirement sequence

[Zhang, Hawking]

[AMD Official Use Only - Internal Distribution Only]

I see. So it's the following programming that is in risk to corrupt data for other instances.

                /* clear umc status */
                WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);

For error injection, everytime it should just have one instance had the error status record. Therefore, it make sense to me that we only clear the status register once. As discussed, we shall also follow up with umc team on the potential issue with index mode programming.

Please also add some comments in code for this unexpected behavior that we shall follow up. Other than that, the patch is

Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>

Regards,
Hawking
From: Clements, John <John.Clements at amd.com>
Sent: Thursday, March 5, 2020 18:19
To: Zhang, Hawking <Hawking.Zhang at amd.com>; amd-gfx at lists.freedesktop.org; Li, Dennis <Dennis.Li at amd.com>; Zhou1, Tao <Tao.Zhou1 at amd.com>; Chen, Guchun <Guchun.Chen at amd.com>
Subject: RE: [PATCH] drm/amdgpu: update page retirement sequence


[AMD Official Use Only - Internal Distribution Only]

In the original sequence, if the key bits are not set in the mca_status, the page retirement will not happen and the status register will be cleared.
If there is a UMC UE, that register will be cleared erroneously 31 times.

If MCA Status == 0 already from the beginning there is no reason to press forward with the rest of the checks and clear the register.

From: Zhang, Hawking <Hawking.Zhang at amd.com<mailto:Hawking.Zhang at amd.com>>
Sent: Thursday, March 5, 2020 5:56 PM
To: Clements, John <John.Clements at amd.com<mailto:John.Clements at amd.com>>; amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>; Li, Dennis <Dennis.Li at amd.com<mailto:Dennis.Li at amd.com>>; Zhou1, Tao <Tao.Zhou1 at amd.com<mailto:Tao.Zhou1 at amd.com>>; Chen, Guchun <Guchun.Chen at amd.com<mailto:Guchun.Chen at amd.com>>
Subject: RE: [PATCH] drm/amdgpu: update page retirement sequence


[AMD Official Use Only - Internal Distribution Only]

Hi John,

Can you please explain more on the differences between (a). exit immediately when mca_status is 0 and (b). exit when some of critical field in mca_status is 0?

Regards,
Hawking
From: Clements, John <John.Clements at amd.com<mailto:John.Clements at amd.com>>
Sent: Thursday, March 5, 2020 17:40
To: amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>; Zhang, Hawking <Hawking.Zhang at amd.com<mailto:Hawking.Zhang at amd.com>>; Li, Dennis <Dennis.Li at amd.com<mailto:Dennis.Li at amd.com>>; Zhou1, Tao <Tao.Zhou1 at amd.com<mailto:Tao.Zhou1 at amd.com>>; Chen, Guchun <Guchun.Chen at amd.com<mailto:Guchun.Chen at amd.com>>
Subject: [PATCH] drm/amdgpu: update page retirement sequence


[AMD Official Use Only - Internal Distribution Only]

check UMC status and exit prior to making and erroneus register access
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