[PATCH v2 4/4] drm/amdgpu/vcn2.5: add sync when WPTR/RPTR reset

[Leo Liu]

On 2020-03-10 3:58 p.m., James Zhu wrote:
> Add vcn harware and firmware synchronization to fix race condition
> issue among vcn driver, hardware and firmware
>
> v2: WA: Add scratch 3 to sync with vcn firmware during W/R pointer reset
>
> Signed-off-by: James Zhu <James.Zhu at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 2d64ba1..9480039 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -1034,6 +1034,9 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
>   		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
>   		WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, tmp);
>   
> +		/* Set scratch3 to start dec/enc registers reset */
> +		WREG32_SOC15(UVD, i, mmUVD_SCRATCH3, 1);
> +
>   		/* programm the RB_BASE for ring buffer */
>   		WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
>   			lower_32_bits(ring->gpu_addr));
> @@ -1059,6 +1062,9 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
>   		WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
>   		WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
>   		WREG32_SOC15(UVD, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
> +
> +		/* Clear scratch3 to finish dec/enc registers reset */
> +		WREG32_SOC15(UVD, i, mmUVD_SCRATCH3, 0);
>   	}
>   
>   	return 0;
> @@ -1388,8 +1394,11 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
>   					   UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
>   					   UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
>   
> +				/* Stall DPG before WPTR/RPTR reset */
> +				WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);

You can wrap up the line shorter? With that fixed, this patch is

Reviewed-by: Leo Liu <leo.liu at amd.com>


Leo


>   				/* Restore */
>   				ring = &adev->vcn.inst[inst_idx].ring_enc[0];
> +				ring->wptr = 0;
>   				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
>   				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
>   				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
> @@ -1397,6 +1406,7 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
>   				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
>   
>   				ring = &adev->vcn.inst[inst_idx].ring_enc[1];
> +				ring->wptr = 0;
>   				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
>   				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
>   				WREG32_SOC15(UVD, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
> @@ -1405,6 +1415,8 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
>   
>   				WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR,
>   					   RREG32_SOC15(UVD, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF);
> +				/* Unstall DPG */
> +				WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
>   
>   				SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS,
>   					   UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);