[PATCH 2/2] drm/amd/amdgpu: Move PWR_MISC_CNTL_STATUS to its own header
Alex Deucher
alexdeucher at gmail.com
Wed Mar 25 18:22:34 UTC 2020
On Wed, Mar 25, 2020 at 2:08 PM Tom St Denis <tom.stdenis at amd.com> wrote:
>
> The register is part of the PWR block not the GC block. Move to
> its own header.
>
> Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> .../amd/include/asic_reg/gc/gc_9_1_offset.h | 2 --
> .../amd/include/asic_reg/gc/gc_9_1_sh_mask.h | 5 ----
> .../include/asic_reg/pwr/pwr_10_0_offset.h | 27 +++++++++++++++++
> .../include/asic_reg/pwr/pwr_10_0_sh_mask.h | 30 +++++++++++++++++++
> 4 files changed, 57 insertions(+), 7 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_sh_mask.h
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
> index ad61ffb0fd97..030e0020902b 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
> @@ -159,8 +159,6 @@
> #define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX 0
> #define mmCP_DE_DE_COUNT 0x00c4
> #define mmCP_DE_DE_COUNT_BASE_IDX 0
> -#define mmPWR_MISC_CNTL_STATUS 0x0183
> -#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
> #define mmCP_STALLED_STAT3 0x019c
> #define mmCP_STALLED_STAT3_BASE_IDX 0
> #define mmCP_STALLED_STAT1 0x019d
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
> index 6cc63562fd55..13bfc2e6e16f 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
> @@ -801,11 +801,6 @@
> //CP_DE_DE_COUNT
> #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
> #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
> -//PWR_MISC_CNTL_STATUS
> -#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
> -#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
> -#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
> -#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
> //CP_STALLED_STAT3
> #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
> #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h
> new file mode 100644
> index 000000000000..e87c359ea1fe
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_offset.h
> @@ -0,0 +1,27 @@
> +/*
> + * Copyright (C) 2020 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included
> + * in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
> + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> + */
> +#ifndef _pwr_10_0_OFFSET_HEADER
> +#define _pwr_10_0_OFFSET_HEADER
> +
> +#define mmPWR_MISC_CNTL_STATUS 0x0183
> +#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
> +
> +#endif
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_sh_mask.h
> new file mode 100644
> index 000000000000..8a000c21651c
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/include/asic_reg/pwr/pwr_10_0_sh_mask.h
> @@ -0,0 +1,30 @@
> +/*
> + * Copyright (C) 2020 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included
> + * in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
> + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> + */
> +#ifndef _pwr_10_0_SH_MASK_HEADER
> +#define _pwr_10_0_SH_MASK_HEADER
> +
> +//PWR_MISC_CNTL_STATUS
> +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
> +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
> +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
> +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
> +
> +#endif
> --
> 2.25.1
>
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