[PATCH 4/4] drm/amdgpu: replace ih ip block for vega20 and arcturus

[Felix Kuehling]

This change seems to break the sequence of IP block initialization that 
is special for SRIOV. Is your intention to use the SRIOV sequence for 
bare metal as well? That would be good for simplifying the code but then 
that should be stated in the commit description, or even be done as a 
separate commit.

See this commit for reference:

commit 2d11fd3f5420f71b15158672a8ffa3722b37ebf5
Author: Trigger Huang <Trigger.Huang at amd.com>
Date:   Wed Apr 24 15:23:41 2019 +0800

     drm/amdgpu: initialize PSP before IH under SR-IOV

     In order to support new PSP feature that PSP may provide interface
     to program IH CNTL register, initialize PSP before IH under Vega10
     SR-IOV VF

     Signed-off-by: Trigger Huang <Trigger.Huang at amd.com>
     Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
     Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Regards,
   Felix

On 2020-03-24 17:57, Alex Sierra wrote:
> [Why]
> Vega20 and Arcturus asics use oss 5.0 version.
>
> [How]
> Replace ih ip block by navi10 for vega20 and arcturus.
>
> Signed-off-by: Alex Sierra <alex.sierra at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/soc15.c | 11 ++++++-----
>   1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index aaf02dbb03f7..a38b5a90cd1c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -62,6 +62,7 @@
>   #include "nbio_v7_0.h"
>   #include "nbio_v7_4.h"
>   #include "vega10_ih.h"
> +#include "navi10_ih.h"
>   #include "sdma_v4_0.h"
>   #include "uvd_v7_0.h"
>   #include "vce_v4_0.h"
> @@ -732,9 +733,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
>   				else
>   					amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
>   			}
> -			amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
>   		} else {
> -			amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
>   			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
>   				if (adev->asic_type == CHIP_VEGA20)
>   					amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
> @@ -742,6 +741,10 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
>   					amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
>   			}
>   		}
> +		if (adev->asic_type == CHIP_VEGA20)
> +			amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> +		else
> +			amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
>   		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
>   		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
>   		if (is_support_sw_smu(adev)) {
> @@ -785,13 +788,11 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
>   		if (amdgpu_sriov_vf(adev)) {
>   			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
>   				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
> -			amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
>   		} else {
> -			amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
>   			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
>   				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
>   		}
> -
> +		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
>   		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
>   			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
>   		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);