[PATCH] Revert "Revert "drm/amdgpu: use the BAR if possible in amdgpu_device_vram_access v2""

[Russell, Kent]

[AMD Official Use Only - Internal Distribution Only]

I will do that instead. Thanks for the recommendation!

 Kent

> -----Original Message-----
> From: Alex Deucher <alexdeucher at gmail.com>
> Sent: Tuesday, May 5, 2020 3:20 PM
> To: Russell, Kent <Kent.Russell at amd.com>
> Cc: amd-gfx list <amd-gfx at lists.freedesktop.org>
> Subject: Re: [PATCH] Revert "Revert "drm/amdgpu: use the BAR if possible in
> amdgpu_device_vram_access v2""
> 
> On Tue, May 5, 2020 at 2:57 PM Kent Russell <kent.russell at amd.com> wrote:
> >
> > This reverts commit e71391880aa72709fac53f98d96a2d4e8875b9fa.
> >
> > The RAS issue at the base of this problem appears to have been
> > addressed
> >
> > Signed-off-by: Kent Russell <kent.russell at amd.com>
> > Change-Id: I338a985e19cae8e103bd44b0f238314e9460d396
> 
> Would probably be cleaner to just re-apply the original patch with an
> additional note in the commit than to revert the revert.  Either way:
> Acked-by: Alex Deucher <alexander.deucher at amd.com>
> 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26
> > ++++++++++++++++++++++
> >  1 file changed, 26 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index caa38e7d502e..bf302c799832 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -255,6 +255,32 @@ void amdgpu_device_vram_access(struct
> amdgpu_device *adev, loff_t pos,
> >         uint32_t hi = ~0;
> >         uint64_t last;
> >
> > +
> > +#ifdef CONFIG_64BIT
> > +       last = min(pos + size, adev->gmc.visible_vram_size);
> > +       if (last > pos) {
> > +               void __iomem *addr = adev->mman.aper_base_kaddr + pos;
> > +               size_t count = last - pos;
> > +
> > +               if (write) {
> > +                       memcpy_toio(addr, buf, count);
> > +                       mb();
> > +                       amdgpu_asic_flush_hdp(adev, NULL);
> > +               } else {
> > +                       amdgpu_asic_invalidate_hdp(adev, NULL);
> > +                       mb();
> > +                       memcpy_fromio(buf, addr, count);
> > +               }
> > +
> > +               if (count == size)
> > +                       return;
> > +
> > +               pos += count;
> > +               buf += count / 4;
> > +               size -= count;
> > +       }
> > +#endif
> > +
> >         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
> >         for (last = pos + size; pos < last; pos += 4) {
> >                 uint32_t tmp = pos >> 31;
> > --
> > 2.17.1
> >
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