[PATCH] drm/amdgpu: turn back rlcg write for gfx_v10

[Liu, Shaoyun]

[AMD Public Use]


[AMD Public Use]

Hi, YinTao
The write to CSIB register through RLCG requires RLCG firmware to support it.  This currently only implemented by nv12 . So you need to find a way to block it  for other GFX 10 asic like NV14 , nv21 if you want to revert the code.

On existing code , amdgpu_mm_wreg_mmio_rlc  seems do what is expected (fall back to MMIO if RLCG support not there) from the name , so although it originally designed for debugfs case access,  we should check why it failed on your case .
In my previous fix , I try to only initialize the rlcg_write function pointer for nv12. The function amdgpu_mm_wreg_mmio_rlc  will depends on SRIOV and rlcg_write function to go through rlcg way .  This will exclude the bare-metal mode . Do you see the  issue on bare metal mode on nv12 ? If that's the case  we might can consider to remove the SRIOV check inside function amdgpu_mm_wreg_mmio_rlc .

Regards
Shaoyun.liu


From: Deucher, Alexander <Alexander.Deucher at amd.com>
Sent: Tuesday, May 12, 2020 10:26 AM
To: Tao, Yintian <Yintian.Tao at amd.com>; Liu, Monk <Monk.Liu at amd.com>; Liu, Shaoyun <Shaoyun.Liu at amd.com>
Cc: amd-gfx at lists.freedesktop.org; Tao, Yintian <Yintian.Tao at amd.com>
Subject: Re: [PATCH] drm/amdgpu: turn back rlcg write for gfx_v10


[AMD Public Use]

Acked-by: Alex Deucher <alexander.deucher at amd.com<mailto:alexander.deucher at amd.com>>
________________________________
From: Yintian Tao <yttao at amd.com<mailto:yttao at amd.com>>
Sent: Tuesday, May 12, 2020 6:17 AM
To: Deucher, Alexander <Alexander.Deucher at amd.com<mailto:Alexander.Deucher at amd.com>>; Liu, Monk <Monk.Liu at amd.com<mailto:Monk.Liu at amd.com>>; Liu, Shaoyun <Shaoyun.Liu at amd.com<mailto:Shaoyun.Liu at amd.com>>
Cc: amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org> <amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>>; Tao, Yintian <Yintian.Tao at amd.com<mailto:Yintian.Tao at amd.com>>
Subject: [PATCH] drm/amdgpu: turn back rlcg write for gfx_v10

There is no need to use amdgpu_mm_wreg_mmio_rlc()
during initialization time because this interface
is only designed for debugfs case to access the
registers which are only permitted by RLCG during
run-time. Therefore, turn back rlcg write for gfx_v10.
If we not turn back it, it will raise amdgpu load failure.
[   54.904333] amdgpu: SMU driver if version not matched
[   54.904393] amdgpu: SMU is initialized successfully!
[   54.905971] [drm] kiq ring mec 2 pipe 1 q 0
[   55.115416] amdgpu 0000:00:06.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring gfx_0.0.0 test failed (-110)
[   55.118877] [drm:amdgpu_device_init [amdgpu]] *ERROR* hw_init of IP block <gfx_v10_0> failed -110
[   55.126587] amdgpu 0000:00:06.0: amdgpu_device_ip_init failed
[   55.133466] amdgpu 0000:00:06.0: Fatal error during GPU init

Signed-off-by: Yintian Tao <yttao at amd.com<mailto:yttao at amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 449408cfd018..bd5dd4f64311 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4577,13 +4577,11 @@ static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);

         /* csib */
-       /* amdgpu_mm_wreg_mmio_rlc will fall back to mmio if doesn't support rlcg_write */
-       amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
-                                adev->gfx.rlc.clear_state_gpu_addr >> 32, 0);
-       amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
-                                adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc, 0);
-       amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
-                                adev->gfx.rlc.clear_state_size, 0);
+       WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
+                        adev->gfx.rlc.clear_state_gpu_addr >> 32);
+       WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
+                        adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
+       WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);

         return 0;
 }
@@ -5192,7 +5190,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
-       amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL), tmp, 0);
+       WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);

         for (i = 0; i < adev->usec_timeout; i++) {
                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
--
2.17.1
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