[PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.

[Alex Deucher]

On Thu, May 21, 2020 at 3:53 PM Gavin Wan <Gavin.Wan at amd.com> wrote:
>
> For SRIOV, since the CGCG is set on host side. The Guest should
> not program CGCG again.
>
> The patch ignores setting CGCG for SRIOV.
>
> Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
> Signed-off-by: Gavin Wan <Gavin.Wan at amd.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index bd5dd4f64311..52b6e4759cf3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
>  static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
>                                                bool enable)
>  {
> +       if (amdgpu_sriov_vf(adev))
> +               return;
> +
>         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
>
>         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
> @@ -6842,6 +6845,9 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
>  {
>         uint32_t data, def;
>
> +       if (amdgpu_sriov_vf(adev))
> +               return;
> +
>         /* It is disabled by HW by default */
>         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
>                 /* 0 - Disable some blocks' MGCG */
> @@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
>  {
>         uint32_t data, def;
>
> +       if (amdgpu_sriov_vf(adev))
> +               return;
> +
>         /* Enable 3D CGCG/CGLS */
>         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
>                 /* write cmd to clear cgcg/cgls ov */
> @@ -6953,6 +6962,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
>  {
>         uint32_t def, data;
>
> +       if (amdgpu_sriov_vf(adev))
> +               return;
> +
>         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
>                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
>                 /* unset CGCG override */
> @@ -6994,6 +7006,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
>  static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
>                                             bool enable)
>  {
> +       if (amdgpu_sriov_vf(adev))
> +               return;
> +
>         amdgpu_gfx_rlc_enter_safe_mode(adev);
>
>         if (enable) {
> --
> 2.25.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx