[PATCH] drm/amdgpu/gmc10: program the smallK fragment size

[Zhang, Hawking]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: Thursday, May 28, 2020 04:29
To: amd-gfx list <amd-gfx at lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: Re: [PATCH] drm/amdgpu/gmc10: program the smallK fragment size

Ping?

On Fri, May 22, 2020 at 6:17 PM Alex Deucher <alexdeucher at gmail.com> wrote:
>
> Explicitly set the smallk size to 0 (4k).  This is the hw default, but 
> set it anyway just in case something else changed it.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 4 ++++  
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c  | 4 ++++
>  2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> index cc866c367939..6939edfc5232 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
> @@ -181,6 +181,10 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
>         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
>         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
>         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
> +
> +       tmp = mmGCVM_L2_CNTL5_DEFAULT;
> +       tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
> +       WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
>  }
>
>  static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device 
> *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> index fb3f228458e5..616309e85d6e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> @@ -164,6 +164,10 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
>         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
>         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
>         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
> +
> +       tmp = mmMMVM_L2_CNTL5_DEFAULT;
> +       tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
> +       WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
>  }
>
>  static void mmhub_v2_0_enable_system_domain(struct amdgpu_device 
> *adev)
> --
> 2.25.4
>
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