[PATCH] drm/amd/amdgpu: specify the power strategy for vcn use

Wang, Kevin(Yang) Kevin1.Wang at amd.com
Tue Nov 3 08:19:29 UTC 2020


comment inline.

________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Kenneth Feng <kenneth.feng at amd.com>
Sent: Tuesday, November 3, 2020 4:07 PM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Feng, Kenneth <Kenneth.Feng at amd.com>
Subject: [PATCH] drm/amd/amdgpu: specify the power strategy for vcn use

The power/performance control strategy is specific for vcn use case.
Then this can optimize the power/performance when the workload is on vcn.

Signed-off-by: Kenneth Feng <kenneth.feng at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 0145504e408b..2c3e111bab43 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -361,6 +361,8 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
                 amdgpu_gfx_off_ctrl(adev, true);
                 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
                        AMD_PG_STATE_GATE);
+               amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
+                               false);
[kevin]:
we'd better to check the return value here, if we really don't care the result, we can print a warning log for debug later.

the patch is:
Reviewed-by: Kevin Wang <kevin1.wang at amd.com>

         } else {
                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
         }
@@ -372,8 +374,11 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)

         atomic_inc(&adev->vcn.total_submission_cnt);

-       if (!cancel_delayed_work_sync(&adev->vcn.idle_work))
+       if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
                 amdgpu_gfx_off_ctrl(adev, false);
+               amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
+                               true);
+       }

         mutex_lock(&adev->vcn.vcn_pg_lock);
         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
--
2.17.1

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