[PATCH 3/3] drm/amdgpu: enable only one compute queue for raven

[Alex Deucher]

On Mon, Nov 9, 2020 at 1:12 PM Nirmoy Das <nirmoy.das at amd.com> wrote:
>
> Because of firmware bug, Raven asics can't handle jobs
> scheduled to multiple compute queues. So enable only one
> compute queue till we have a firmware fix.
>
> Signed-off-by: Nirmoy Das <nirmoy.das at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 97a8f786cf85..9352fcb77fe9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -812,6 +812,13 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
>  int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
>  {
>         if (amdgpu_num_kcq == -1) {
> +               /* raven firmware currently can not load balance jobs
> +                * among multiple compute queues. Enable only one
> +                * compute queue till we have a firmware fix.
> +                */
> +               if (adev->asic_type == CHIP_RAVEN)
> +                       return 1;
> +

I think this is fine as a workaround for now, but it would be worth
checking is the issues are only between queues on the same pipe or
pipes on an MEC.  E.g., can we safely enable one queue per MEC?  What
about one queue per pipe?

Alex


>                 return 8;
>         } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
>                 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
> --
> 2.29.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx