[PATCH] drm/amd/display: Tune fclk for 4K OLED display

[Wu, Hersen]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Hersen Wu <hersenxs.wu at amd.com>


-----Original Message-----
From: Vishwakarma, Pratik <Pratik.Vishwakarma at amd.com> 
Sent: Monday, November 9, 2020 12:39 AM
To: Wu, Hersen <hersenxs.wu at amd.com>; amd-gfx at lists.freedesktop.org
Cc: Vishwakarma, Pratik <Pratik.Vishwakarma at amd.com>
Subject: [PATCH] drm/amd/display: Tune fclk for 4K OLED display

[Why]
On 4K SKU, in DC mode, there is a visible slowness observed on system compared to AC mode.

[How]
Tuning min fclk up by 2% resolved this issue.

Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma at amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c   | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index 832a43053420..ead009628c48 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -210,6 +210,7 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
 	bool send_request_to_increase = false;
 	bool send_request_to_lower = false;
 	int display_count;
+	int i, clock_factor = 0;
 
 	bool enter_display_off = false;
 
@@ -217,6 +218,12 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
 
 	pp_smu = &clk_mgr->pp_smu->rv_funcs;
 
+	for (i = 0; i < context->stream_count; i++) {
+		if (context->streams[i]->timing.h_total > 3840
+			|| context->streams[i]->timing.v_total > 2160)
+			clock_factor = 2;
+	}
+
 	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
 
 	if (display_count == 0)
@@ -302,7 +309,7 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
 						(new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
 			} else {
 				pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
-						new_clocks->fclk_khz / 1000);
+						((new_clocks->fclk_khz / 1000) * (100 + clock_factor)) / 100);
 				pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
 						new_clocks->dcfclk_khz / 1000);
 				pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
--
2.25.1