[PATCH 2/5] drm/amdgpu: add amdgpu_gfx_state_change_set() set gfx power change entry
Alex Deucher
alexdeucher at gmail.com
Thu Nov 12 19:48:52 UTC 2020
On Thu, Nov 12, 2020 at 2:06 AM Prike Liang <Prike.Liang at amd.com> wrote:
>
> The new amdgpu_gfx_state_change_set() funtion can support set GFX power
> change status to D0/D3.
>
> Signed-off-by: Prike Liang <Prike.Liang at amd.com>
> Acked-by: Huang Rui <ray.huang at amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 20 ++++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 7 +++++++
> drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
> drivers/gpu/drm/amd/pm/inc/hwmgr.h | 1 +
> drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h | 3 ++-
> drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 19 +++++++++++++++++++
> drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 10 ++++++++++
> 7 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 97a8f78..380dd3a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -819,3 +819,23 @@ int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
> }
> return amdgpu_num_kcq;
> }
> +
> +/* amdgpu_gfx_state_change_set - Handle gfx power state change set
> + * @adev: amdgpu_device pointer
> + * @state: gfx power state(1 -sGpuChangeState_D0Entry and 2 -sGpuChangeState_D3Entry)
> + *
> + */
> +
> +void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state)
> +{
> +
> + mutex_lock(&adev->pm.mutex);
pm.mutex is only relevant for the powerplay case. swSMU uses
different locking. Move the mutexes into the if clause.
Alex
> +
> + if (adev->powerplay.pp_funcs &&
> + adev->powerplay.pp_funcs->gfx_state_change_set)
> + ((adev)->powerplay.pp_funcs->gfx_state_change_set(
> + (adev)->powerplay.pp_handle, state));
> +
> + mutex_unlock(&adev->pm.mutex);
> +
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 671d4b3..6b5a8f4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -47,6 +47,12 @@ enum gfx_pipe_priority {
> AMDGPU_GFX_PIPE_PRIO_MAX
> };
>
> +/* Argument for PPSMC_MSG_GpuChangeState */
> +enum gfx_change_state {
> + sGpuChangeState_D0Entry = 1,
> + sGpuChangeState_D3Entry,
> +};
> +
> #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
> #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
>
> @@ -394,4 +400,5 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
> uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
> void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
> int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
> +void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state);
> #endif
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 94132c7..f775aac 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -285,6 +285,7 @@ struct amd_pm_funcs {
> int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
> int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
> int (*smu_i2c_bus_access)(void *handle, bool acquire);
> + int (*gfx_state_change_set)(void *handle, uint32_t state);
> /* export to DC */
> u32 (*get_sclk)(void *handle, bool low);
> u32 (*get_mclk)(void *handle, bool low);
> diff --git a/drivers/gpu/drm/amd/pm/inc/hwmgr.h b/drivers/gpu/drm/amd/pm/inc/hwmgr.h
> index 7e29ec2..1bb3794 100644
> --- a/drivers/gpu/drm/amd/pm/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/pm/inc/hwmgr.h
> @@ -366,6 +366,7 @@ struct pp_hwmgr_func {
> int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr,
> bool disable);
> ssize_t (*get_gpu_metrics)(struct pp_hwmgr *hwmgr, void **table);
> + int (*gfx_state_change)(struct pp_hwmgr *hwmgr, uint32_t state);
> };
>
> struct pp_table_func {
> diff --git a/drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h
> index df4677d..4c7e08b 100644
> --- a/drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h
> +++ b/drivers/gpu/drm/amd/pm/inc/rv_ppsmc.h
> @@ -83,7 +83,8 @@
> #define PPSMC_MSG_SetSoftMaxVcn 0x34
> #define PPSMC_MSG_PowerGateMmHub 0x35
> #define PPSMC_MSG_SetRccPfcPmeRestoreRegister 0x36
> -#define PPSMC_Message_Count 0x37
> +#define PPSMC_MSG_GpuChangeState 0x37
> +#define PPSMC_Message_Count 0x42
>
> typedef uint16_t PPSMC_Result;
> typedef int PPSMC_Msg;
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> index eab9768..e0d2882 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> @@ -1629,6 +1629,24 @@ static ssize_t pp_get_gpu_metrics(void *handle, void **table)
> return size;
> }
>
> +static int pp_gfx_state_change_set(void *handle, uint32_t state)
> +{
> + struct pp_hwmgr *hwmgr = handle;
> +
> + if (!hwmgr || !hwmgr->pm_en)
> + return -EINVAL;
> +
> + if (hwmgr->hwmgr_func->gfx_state_change == NULL) {
> + pr_info_ratelimited("%s was not implemented.\n", __func__);
> + return -EINVAL;
> + }
> +
> + mutex_lock(&hwmgr->smu_lock);
> + hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
> + mutex_unlock(&hwmgr->smu_lock);
> + return 0;
> +}
> +
> static const struct amd_pm_funcs pp_dpm_funcs = {
> .load_firmware = pp_dpm_load_fw,
> .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
> @@ -1691,4 +1709,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
> .set_df_cstate = pp_set_df_cstate,
> .set_xgmi_pstate = pp_set_xgmi_pstate,
> .get_gpu_metrics = pp_get_gpu_metrics,
> + .gfx_state_change_set = pp_gfx_state_change_set,
> };
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> index 133a084..50308a5 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1439,6 +1439,15 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
> return 0;
> }
>
> +static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state)
> +{
> + struct amdgpu_device *adev = hwmgr->adev;
> +
> + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState, state, NULL);
> +
> + return 0;
> +}
> +
> static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
> .backend_init = smu10_hwmgr_backend_init,
> .backend_fini = smu10_hwmgr_backend_fini,
> @@ -1485,6 +1494,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
> .set_power_profile_mode = smu10_set_power_profile_mode,
> .asic_reset = smu10_asic_reset,
> .set_fine_grain_clk_vol = smu10_set_fine_grain_clk_vol,
> + .gfx_state_change = smu10_gfx_state_change,
> };
>
> int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
> --
> 2.7.4
>
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