[PATCH 2/2] drm/amd/pm: fix the crash after runtime pm resume

Quan, Evan Evan.Quan at amd.com
Wed Nov 18 00:45:52 UTC 2020


[AMD Official Use Only - Internal Distribution Only]

I suspect "smu_is_dpm_running" reports a wrong result due to "smu_system_features_control(smu, false)" was skipped for SIENNA_CICHLID in smu_disable_dpms().
That is outdated cached values were used for "smu_is_dpm_running".
If that's true, a fix in smu_disable_dpms() may be more proper.

Evan
-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Kenneth Feng
Sent: Tuesday, November 17, 2020 9:31 PM
To: amd-gfx at lists.freedesktop.org
Cc: Feng, Kenneth <Kenneth.Feng at amd.com>
Subject: [PATCH 2/2] drm/amd/pm: fix the crash after runtime pm resume

Some features are still disabled after runtime pm resume. This can take the hardware back.
Unlike other projects, this doesn't need pptable retransfer.

Signed-off-by: Kenneth Feng <kenneth.feng at amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 39990790ed67..ebd50f144c5d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -914,11 +914,14 @@ static int smu_smc_hw_setup(struct smu_context *smu)  {
 struct amdgpu_device *adev = smu->adev;
 uint32_t pcie_gen = 0, pcie_width = 0;
-int ret;
+int ret = 0;

 if (adev->in_suspend && smu_is_dpm_running(smu)) {
 dev_info(adev->dev, "dpm has been enabled\n");
-return 0;
+/* this is needed specifically */
+if (adev->asic_type == CHIP_SIENNA_CICHLID)
+ret = smu_system_features_control(smu, true);
+return ret;
 }

 ret = smu_init_display_count(smu, 0);
--
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx at lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cevan.quan%40amd.com%7Cdd553fd04f0f44ebf3ca08d88afd11ad%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637412166811942772%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=SgtA0lq6Sx5aiQ5PSLvf9GdXUU50cFLE5ELMY0e8k5g%3D&reserved=0


More information about the amd-gfx mailing list