[PATCH] drm/amd/pm: support runtime PPTable update for dimgrey_cavefish

[Chen, Jiansong (Simon)]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Jiansong Chen <Jiansong.Chen at amd.com>

-----Original Message-----
From: Zhou1, Tao <Tao.Zhou1 at amd.com>
Sent: Tuesday, November 17, 2020 3:33 PM
To: Chen, Jiansong (Simon) <Jiansong.Chen at amd.com>; Gui, Jack <Jack.Gui at amd.com>; Zhang, Hawking <Hawking.Zhang at amd.com>; amd-gfx at lists.freedesktop.org
Cc: Zhou1, Tao <Tao.Zhou1 at amd.com>
Subject: [PATCH] drm/amd/pm: support runtime PPTable update for dimgrey_cavefish

There is no need to reset DPM for PPTable uploading on dimgrey_cavefish and PMFW can handle it, same as navy_flounder.

Signed-off-by: Tao Zhou <tao.zhou1 at amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 1904df5a3e20..8e3e7a5bbffe 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1183,7 +1183,7 @@ static int smu_disable_dpms(struct smu_context *smu)
  */
 if (smu->uploading_custom_pp_table &&
     (adev->asic_type >= CHIP_NAVI10) &&
-    (adev->asic_type <= CHIP_NAVY_FLOUNDER))
+    (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
 return 0;

 /*
--
2.17.1