[PATCH] drm/amdgpu: update GC golden setting for navy_flounder

[Zhou1, Tao]

[AMD Public Use]

Reviewed-by: Tao Zhou <tao.zhou1 at amd.com>

> -----Original Message-----
> From: Jiansong Chen <Jiansong.Chen at amd.com>
> Sent: Monday, November 23, 2020 11:27 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Zhou1, Tao <Tao.Zhou1 at amd.com>; Chen, Jiansong (Simon)
> <Jiansong.Chen at amd.com>
> Subject: [PATCH] drm/amdgpu: update GC golden setting for navy_flounder
> 
> Update GC golden setting for navy_flounder.
> 
> Signed-off-by: Jiansong Chen <Jiansong.Chen at amd.com>
> Change-Id: I25d5afb46ef9667a65bc897dcddf54390891e90f
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index eb05d1bc194e..841d39eb62d9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3191,6 +3191,7 @@ static const struct soc15_reg_golden
> golden_settings_gc_10_3_sienna_cichlid[] =
> 
>  static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =  {
> +	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL,
> 0xff7f0fff,
> +0x78000100),
>  	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL,
> 0xff7f0fff, 0x78000100),
>  	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL,
> 0xff7f0fff, 0x30000100),
>  	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL,
> 0xff7f0fff, 0x7e000100), @@ -3199,6 +3200,8 @@ static const struct
> soc15_reg_golden golden_settings_gc_10_3_2[] =
>  	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff,
> 0x00800000),
>  	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL,
> 0x7fff0f1f, 0x00b80000),
>  	SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
> +	SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
> +	SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid,
> +0xffff8fff, 0xff008080),
>  	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff,
> 0x00280400),
>  	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK,
> 0xffffffff, 0xffffffcf),
>  	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK,
> 0xffffffff, 0xffffffcf),
> --
> 2.25.1