[PATCH 2/2] drm/amdgpu: enable only one compute queue for raven

Nirmoy nirmodas at amd.com
Wed Oct 14 15:46:02 UTC 2020


Please ignore this patch, it didn't workaround the fw bug.


Regards,

Nirmoy

On 10/14/20 3:52 PM, Nirmoy Das wrote:
> Because of firmware bug, Raven asics can't handle jobs
> scheduled to multiple compute queues. So enable only one
> compute queue till we have a firmware fix.
>
> Signed-off-by: Nirmoy Das <nirmoy.das at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c |  4 ++++
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 11 ++++++++++-
>   2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 8c9bacfdbc30..ca2ac985b300 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -195,6 +195,10 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
>   bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
>   					       int queue)
>   {
> +	/* We only enable one compute queue for Raven */
> +	if (adev->asic_type == CHIP_RAVEN)
> +		return false;
> +
>   	/* Policy: make queue 0 of each pipe as high priority compute queue */
>   	return (queue == 0);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 0d8e203b10ef..f3fc9ad8bc20 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4633,7 +4633,16 @@ static int gfx_v9_0_early_init(void *handle)
>   		adev->gfx.num_gfx_rings = 0;
>   	else
>   		adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
> -	adev->gfx.num_compute_rings = amdgpu_num_kcq;
> +
> +	/* raven firmware currently can not load balance jobs
> +	 * among multiple compute queues. Enable only one
> +	 * compute queue till we have a firmware fix.
> +	 */
> +	if (adev->asic_type == CHIP_RAVEN)
> +		adev->gfx.num_compute_rings = 1;
> +	else
> +		adev->gfx.num_compute_rings = amdgpu_num_kcq;
> +
>   	gfx_v9_0_set_kiq_pm4_funcs(adev);
>   	gfx_v9_0_set_ring_funcs(adev);
>   	gfx_v9_0_set_irq_funcs(adev);


More information about the amd-gfx mailing list