[PATCH 08/40] drm/amd/pm: correct the BootLinkLevel setup
Evan Quan
evan.quan at amd.com
Fri Oct 16 03:26:20 UTC 2020
Set the BootLinkLevel as the max level.
Change-Id: I5fde6b472c9d802420be5783fd93f589404e66eb
Signed-off-by: Evan Quan <evan.quan at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
---
drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
index a6c8f121f41c..d9d53fbd438d 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
@@ -2023,7 +2023,7 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
table->VoltageResponseTime = 0;
table->PhaseResponseTime = 0;
table->MemoryThermThrottleEnable = 1;
- table->PCIeBootLinkLevel = 0;
+ table->PCIeBootLinkLevel = hw_data->dpm_table.pcie_speed_table.count;
table->PCIeGenInterval = 1;
table->VRConfig = 0;
--
2.28.0
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