[PATCH] drm/amd/pm: fix pcie information for sienna cichlid

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng <kenneth.feng at amd.com>


在 2020/10/20 下午4:57，“Gao, Likun”<Likun.Gao at amd.com> 写入:

    From: Likun Gao <Likun.Gao at amd.com>

    Fix the function used for sienna cichlid to get correct PCIE information
    by pp_dpm_pcie.

    Signed-off-by: Likun Gao <Likun.Gao at amd.com>
    Change-Id: I81e529be6e96f083eb7aa244c16700422bde5fec
    ---
     drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 ++--
     1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
    index c8e8790e0871..e00c38b1bd41 100644
    --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
    +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
    @@ -964,8 +964,8 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
     }
     break;
     case SMU_PCIE:
    -gen_speed = smu_v11_0_get_current_pcie_link_speed(smu);
    -lane_width = smu_v11_0_get_current_pcie_link_width(smu);
    +gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
    +lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
     for (i = 0; i < NUM_LINK_LEVELS; i++)
     size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
     (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
    --
    2.25.1