[PATCH] drm/amd/display: Initialize num_pkrs on VANGOGH.

[Huang Rui]

On Tue, Oct 20, 2020 at 07:47:42PM -0400, Marek Olšák wrote:
> FYI, this fixes tiling on VanGogh.
> 
> Reviewed-by: Marek Olšák <marek.olsak at amd.com>
> 
> Marek
> 
> On Tue, Oct 20, 2020 at 6:31 PM Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
> wrote:
> 
> > As far a I can tell uses a variant of DCN3xx which uses num_pkrs.
> >
> > If we do not initialize the variable we will set the register field
> > to ilog2(0) = -1, though the mask will reduce that to 7. Pretty sure
> > 7 is not the value we want here.
> >
> > Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
> > ---
> >
> > Found while rebasing my modifiers series. Not tested on HW.

Yes! Thank you so much, Bas!

I just verified the tiling issue got resovled with your patch! :-)

Applied.

Reviewed-and-Tested-by: Huang Rui <ray.huang at amd.com>

> >
> >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 6855aad7f312..2713caac4f2a 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -4074,7 +4074,8 @@ fill_plane_buffer_attributes(struct amdgpu_device
> > *adev,
> >  #ifdef CONFIG_DRM_AMD_DC_DCN3_0
> >                 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
> >                     adev->asic_type == CHIP_NAVY_FLOUNDER ||
> > -                   adev->asic_type == CHIP_DIMGREY_CAVEFISH)
> > +                   adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
> > +                   adev->asic_type == CHIP_VANGOGH)
> >                         tiling_info->gfx9.num_pkrs =
> > adev->gfx.config.gb_addr_config_fields.num_pkrs;
> >  #endif
> >                 ret = fill_plane_dcc_attributes(adev, afb, format,
> > rotation,
> > --
> > 2.28.0
> >
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> >

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