[PATCH 2/3] drm/amdgpu: add support to configure MALL for sienna_cichlid (v2)

[Christian König]

Am 20.10.20 um 22:26 schrieb Alex Deucher:
> From: Likun Gao <Likun.Gao at amd.com>
>
> Enable Memory Access at Last Level (MALL) feature for sienna_cichlid.
>
> v2: drop module option.  We need to add UAPI so userspace can
> request MALL per buffer.
>
> Signed-off-by: Likun Gao <Likun.Gao at amd.com>
> Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Reviewed-by: Christian König <christian.koenig at amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++
>   drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 ++-
>   drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +-
>   3 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index ffea3b89b9da..929d7cb92dc0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -76,6 +76,9 @@ struct amdgpu_bo_list_entry;
>   /* PTE is handled as PDE for VEGA10 (Translate Further) */
>   #define AMDGPU_PTE_TF		(1ULL << 56)
>   
> +/* MALL noalloc for sienna_cichlid, reserved for older ASICs  */
> +#define AMDGPU_PTE_NOALLOC	(1ULL << 58)
> +
>   /* PDE Block Fragment Size for VEGA10 */
>   #define AMDGPU_PDE_BFS(a)	((uint64_t)a << 59)
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index 40af17610207..ef385a529013 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -486,7 +486,8 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid
>   /*
>    * PTE format on NAVI 10:
>    * 63:59 reserved
> - * 58:57 reserved
> + * 58 reserved and for sienna_cichlid is used for MALL noalloc
> + * 57 reserved
>    * 56 F
>    * 55 L
>    * 54 reserved
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index 18eca0d4dbcc..ae6158456094 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -707,7 +707,7 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
>   		temp &= 0xFF0FFF;
>   		temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
>   			 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
> -			 0x01000000);
> +			 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
>   		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
>   
>   		if (!amdgpu_sriov_vf(adev)) {