[PATCH] drm/amdgpu/display: fix 64 bit division in dcn30_hwseq.c

[Alex Deucher]

Use div_u64 helpers.

Reviewed-by: Slava Abramov <slava.abramov at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index a06f6d19e38e..f3ae208850b0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -717,8 +717,10 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
 
 			// TODO: remove hard code size
 			if (surface_size < 128 * 1024 * 1024) {
-				refresh_hz = (unsigned long long) dc->current_state->streams[0]->timing.pix_clk_100hz * 100LL /
-						(dc->current_state->streams[0]->timing.v_total * dc->current_state->streams[0]->timing.h_total);
+				refresh_hz = div_u64((unsigned long long) dc->current_state->streams[0]->timing.pix_clk_100hz *
+						     100LL,
+						     (dc->current_state->streams[0]->timing.v_total *
+						      dc->current_state->streams[0]->timing.h_total));
 
 				/*
 				 * Delay_Us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
@@ -732,7 +734,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
 				 * need to round up the result of the division before the subtraction
 				 */
 				denom = refresh_hz * 6528;
-				tmr_delay = (100000000LL + denom - 1) / denom - 64LL;
+				tmr_delay = div_u64((100000000LL + denom - 1), denom) - 64LL;
 
 				/* scale should be increased until it fits into 6 bits */
 				while (tmr_delay & ~0x3F) {
@@ -745,7 +747,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
 					}
 
 					denom *= 2;
-					tmr_delay = (100000000LL + denom - 1) / denom - 64LL;
+					tmr_delay = div_u64((100000000LL + denom - 1), denom) - 64LL;
 				}
 
 				/* Enable MALL */
-- 
2.25.4