[PATCH 00/25] DC Patches Nov 2nd, 2020

Qingqing Zhuo qingqing.zhuo at amd.com
Tue Oct 27 20:52:09 UTC 2020


This DC patchset brings improvements in multiple areas. In summary, we have:
  * DC 3.2.110
  * Firmware release 0.0.40
  * Enable CRC calculation on specific frame region
  * Bug fixes on GSL, recout calculation, missing pflip irq and more.

---

Alvin Lee (2):
  drm/amd/display: Keep GSL for full updates with planes that flip VSYNC
  drm/amd/display: Reset flip_immediate to topmost plane

Anthony Koo (2):
  drm/amd/display: [FW Promotion] Release 0.0.39
  drm/amd/display: [FW Promotion] Release 0.0.40

Aric Cyr (2):
  drm/amd/display: 3.2.109
  drm/amd/display: 3.2.110

Ashley Thomas (1):
  drm/amd/display: fail instead of div by zero/bugcheck

Bhawanpreet Lakha (1):
  drm/amd/display: Add missing pflip irq

Chris Park (1):
  drm/amd/display: Update panel register

Dale Zhao (1):
  drm/amd/display: WA to ensure MUX chip gets SUPPORTED_LINK_RATES of
    eDP

Dmytro Laktyushkin (1):
  drm/amd/display: fix recout calculation for left side clip

Eryk Brol (1):
  drm/amd/display: Update connector on DSC property change

Hugo Hu (1):
  drm/amd/display: correct eDP T9 delay

Isabel Zhang (1):
  drm/amd/display: Force prefetch mode to 0

Jacky Liao (2):
  drm/amd/display: Add MPC memory shutdown support for DCN3
  drm/amd/display: Add OPTC memory low power support

Jake Wang (1):
  drm/amd/display: set hdcp1 wa re-auth delay to 200ms

Joshua Aberback (3):
  drm/amd/display: Blank HUBP during pixel data blank for DCN30
  drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2
  drm/amd/display: Revert HUBP blank behaviour for now

Lewis Huang (1):
  drm/amd/display: stop top_mgr when type change to non-MST during s3

Tao.Huang (1):
  drm/amd/display: Fix compilation error

Victor Lu (1):
  drm/amd/display: Do not warn NULL dc_sink if forcing connector

Wayne Lin (1):
  drm/amd/display: Calculate CRC on specific frame region

Yongqiang Sun (1):
  drm/amd/display: only check available pipe to disable vbios mode.

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   9 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   1 +
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c |   2 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 124 ++++++++++++++++++
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  21 ++-
 .../gpu/drm/amd/display/dc/core/dc_debug.c    |   2 +
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  12 ++
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  72 +++++-----
 .../drm/amd/display/dc/core/dc_link_hwss.c    |  13 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   4 +
 drivers/gpu/drm/amd/display/dc/dc.h           |  11 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |   1 +
 .../gpu/drm/amd/display/dc/dce/dce_hwseq.h    |  12 +-
 .../display/dc/dce110/dce110_hw_sequencer.c   |  16 +--
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  42 +++++-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.h    |   9 ++
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   1 +
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |   1 +
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |   4 +-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h  |   2 +-
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    |  18 +++
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.h    |   8 ++
 .../gpu/drm/amd/display/dc/dcn30/dcn30_init.c |   1 +
 .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c  |  56 +++++++-
 .../gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h  |   9 ++
 .../amd/display/dc/dcn302/dcn302_resource.c   |   2 +-
 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c  |   6 +-
 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h  |   4 +-
 .../gpu/drm/amd/display/dc/inc/core_status.h  |   1 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   8 ++
 .../gpu/drm/amd/display/dc/inc/link_hwss.h    |   1 +
 .../display/dc/irq/dcn30/irq_service_dcn30.c  |   4 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  11 +-
 .../display/modules/hdcp/hdcp1_transition.c   |   2 +-
 34 files changed, 418 insertions(+), 72 deletions(-)

-- 
2.17.1



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