[PATCH 11/25] drm/amd/display: Update panel register

[Qingqing Zhuo]

From: Chris Park <Chris.Park at amd.com>

[Why]
Incorrect panel register settings are
applied for power sequence because the
register macro is not defined in resource.

[How]
Implement same register space to future
resource files.

Signed-off-by: Chris Park <Chris.Park at amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback at amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo at amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index c4ffed95d35e..2345f12ceab3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -967,7 +967,7 @@ static const struct encoder_feature_support link_enc_feature = {
 		[id] = {\
 				LE_DCN3_REG_LIST(id), \
 				UNIPHY_DCN2_REG_LIST(phyid), \
-				DPCS_DCN2_REG_LIST(id), \
+				SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 		}
 
 static const struct dcn10_link_enc_registers link_enc_regs[] = {
-- 
2.17.1