[PATCH] drm/amd/pm: add the reset function of the pp_od_voltage_clk sysfs file for RV/RV2/PCO APU

[Alex Deucher]

On Thu, Oct 29, 2020 at 11:04 PM Xiaojian Du <Xiaojian.Du at amd.com> wrote:
>
> From: Xiaojian Du <xiaojian.du at amd.com>
>
> From: Xiaojian Du <Xiaojian.Du at amd.com>
>
> This patch is to add the reset function of the pp_od_voltage_clk sysfs
> file for Raven/Raven2/Picasso APU.
> If the min and max sclk frequence are configured, this function can
> be used to restore the default sclk frequence.

typo: frequency

>
> Command guide:
> echo "r" > pp_od_clk_voltage
>         r - reset the sclk level

Not directly related to your patch, but for consistency, we should
only apply the changes when the user sends the 'c' parameter.  That
way you can queue up all the changes before they are applied.

Alex

>
> Example:
> 1) check the default sclk frequence
>         $ cat pp_od_clk_voltage
>         OD_SCLK:
>         0:        200Mhz
>         1:       1400Mhz
>         OD_RANGE:
>         SCLK:     200MHz       1400MHz
> 2) use "s" -- set command to configure the min or max sclk frequence
>         $ echo "s 0 600" > pp_od_clk_voltage
>         $ echo "s 1 1000" > pp_od_clk_voltage
>         $ cat pp_od_clk_voltage
>         OD_SCLK:
>         0:        600Mhz
>         1:       1000Mhz
>         OD_RANGE:
>         SCLK:     200MHz       1400MHz
> 3) use "r" -- reset command to restore the default sclk frequence range
>         $ echo "r" > pp_od_clk_voltage
>         $ cat pp_od_clk_voltage
>         OD_SCLK:
>         0:        200Mhz
>         1:       1400Mhz
>         OD_RANGE:
>         SCLK:     200MHz       1400MHz
>
> Signed-off-by: Xiaojian Du <Xiaojian.Du at amd.com>
> ---
>  .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c  | 32 ++++++++++++++-----
>  1 file changed, 24 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> index cf60f3992303..bbe7f101acbf 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1421,18 +1421,34 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
>                 return -EINVAL;
>         }
>
> -       if (size != 2) {
> -               pr_err("Input parameter number not correct\n");
> -               return -EINVAL;
> -       }
> -
>         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
> -               if (input[0] == 0)
> +               if (size != 2) {
> +                       pr_err("Input parameter number not correct\n");
> +                       return -EINVAL;
> +               }
> +
> +               if (input[0] == 0) {
>                         smu10_set_hard_min_gfxclk_by_freq(hwmgr, input[1]);
> -               else if (input[0] == 1)
> +               } else if (input[0] == 1) {
>                         smu10_set_soft_max_gfxclk_by_freq(hwmgr, input[1]);
> -               else
> +               } else {
>                         return -EINVAL;
> +               }
> +       } else if (type == PP_OD_RESTORE_DEFAULT_TABLE) {
> +               if (size != 0) {
> +                       pr_err("Input parameter number not correct\n");
> +                       return -EINVAL;
> +               }
> +
> +               uint32_t min_freq, max_freq = 0;
> +
> +               smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
> +               smu10_set_hard_min_gfxclk_by_freq(hwmgr, min_freq);
> +               smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
> +               smu10_set_soft_max_gfxclk_by_freq(hwmgr, max_freq);
> +
> +       } else {
> +               return -EINVAL;
>         }
>
>         return 0;
> --
> 2.17.1
>
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