[PATCH] drm/amdgpu: apply dm_pp_notify_wm_clock_changes() for Polaris only
Christian König
christian.koenig at amd.com
Fri Oct 30 11:06:20 UTC 2020
Am 30.10.20 um 12:04 schrieb Evan Quan:
> Will expand it to other ASICs after verified.
>
> Change-Id: I03e074ea0e921a984eb819b222e434e88888e375
> Signed-off-by: Evan Quan <evan.quan at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
I assume this fixes my issue on Vega20?
Thanks,
Christian.
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index fd39dd67bfa4..84065c12d4b8 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -462,7 +462,12 @@ bool dm_pp_notify_wm_clock_changes(
> void *pp_handle = adev->powerplay.pp_handle;
> const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
>
> - if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges) {
> + /*
> + * Limit this watermark setting for Polaris for now
> + * TODO: expand this to other ASICs
> + */
> + if ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_VEGAM)
> + && pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges) {
> if (!pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
> (void *)wm_with_clock_ranges))
> return true;
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