[PATCH] drm/amd/pm: support runtime pptable update for sienna_cichlid etc.

[Chen, Jiansong (Simon)]

It makes nonsense to call gfxoff  when smu failure has happened.

Regards,
Jiansong
-----Original Message-----
From: Chen, Guchun <Guchun.Chen at amd.com> 
Sent: Monday, September 14, 2020 4:14 PM
To: Chen, Jiansong (Simon) <Jiansong.Chen at amd.com>; amd-gfx at lists.freedesktop.org
Cc: Zhou1, Tao <Tao.Zhou1 at amd.com>; Feng, Kenneth <Kenneth.Feng at amd.com>; Quan, Evan <Evan.Quan at amd.com>; Chen, Jiansong (Simon) <Jiansong.Chen at amd.com>
Subject: RE: [PATCH] drm/amd/pm: support runtime pptable update for sienna_cichlid etc.

[AMD Public Use]

ret = smu_late_init(adev);
+	if (ret)
+		return ret;

One counter leak happens? It needs to call amdgpu_gfx_off_ctrl(smu->adev, true) before returning?

Regards,
Guchun

-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Jiansong Chen
Sent: Monday, September 14, 2020 4:10 PM
To: amd-gfx at lists.freedesktop.org
Cc: Zhou1, Tao <Tao.Zhou1 at amd.com>; Feng, Kenneth <Kenneth.Feng at amd.com>; Quan, Evan <Evan.Quan at amd.com>; Chen, Jiansong (Simon) <Jiansong.Chen at amd.com>
Subject: [PATCH] drm/amd/pm: support runtime pptable update for sienna_cichlid etc.

This avoids smu issue when enabling runtime pptable update for sienna_cichlid and so on. Runtime pptable udpate is needed for test and debug purpose.

Signed-off-by: Jiansong Chen <Jiansong.Chen at amd.com>
Change-Id: I70b704ab4d6efd169f579c392e5dbc2737dc1fb2
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7a55ece1f124..7618f9972b8c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1129,7 +1129,7 @@ static int smu_disable_dpms(struct smu_context *smu)
 	 */
 	if (smu->uploading_custom_pp_table &&
 	    (adev->asic_type >= CHIP_NAVI10) &&
-	    (adev->asic_type <= CHIP_NAVI12))
+	    (adev->asic_type <= CHIP_NAVY_FLOUNDER))
 		return 0;
 
 	/*
@@ -1214,7 +1214,9 @@ static int smu_hw_fini(void *handle)  int smu_reset(struct smu_context *smu)  {
 	struct amdgpu_device *adev = smu->adev;
-	int ret = 0;
+	int ret;
+
+	amdgpu_gfx_off_ctrl(smu->adev, false);
 
 	ret = smu_hw_fini(adev);
 	if (ret)
@@ -1225,8 +1227,12 @@ int smu_reset(struct smu_context *smu)
 		return ret;
 
 	ret = smu_late_init(adev);
+	if (ret)
+		return ret;
 
-	return ret;
+	amdgpu_gfx_off_ctrl(smu->adev, true);
+
+	return 0;
 }
 
 static int smu_suspend(void *handle)
--
2.25.1

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